Engineering threshold analysis

When 4 layers stop being enough: the 6-layer signal integrity threshold

Common engineering scenario

You designed a 4-layer board around an SoC with a DDR3 interface (800 MHz), one GbE PHY, a USB 2.0 host controller, three power domains (3.3 V, 1.8 V, 1.2 V), and an analog sensor front-end. The 4-layer stackup gave you two signal layers and two planes. After layout, you discovered: the DDR address bus could not route on a single layer without layer changes that broke the reference plane. The GbE differential pairs crossed a split in the power plane because there was no room for a dedicated ground island. The analog section picked up 50 MHz digital harmonics from the SoC's PLL, visible at the ADC output. You need another pair of signal-and-plane layers — but only two more, not four.

This is the signal integrity threshold: the point at which a 4-layer board has enough copper layers for the schematic but not enough structural signal integrity for the design to pass pre-compliance testing. The 6-layer PCB exists specifically to solve this problem. It adds one additional signal–plane pair (or two additional routing layers, depending on the stackup architecture), giving you the headroom to dedicate planes to individual power domains, maintain continuous reference planes for high-speed signals, and isolate sensitive analog sections from digital switching noise.

Unlike the jump from 2 to 4 layers — which is a structural shift (adding internal planes where none existed) — the jump from 4 to 6 layers is a signal integrity engineering decision. It is driven by constraints that appear during layout, not schematic capture: return path continuity, layer-change via count, reference plane assignment, and routing channel availability for the highest-speed nets. This page is structured as a diagnostic framework to help you determine whether your design has crossed this threshold, and how to build a 6-layer board that actually solves the problem.

Signal integrity engineering 4-layer to 6-layer upgrade Return path continuity DDR / GbE / USB routing Sequential lamination Via architecture planning

Diagnose your 6-layer requirements Compare 4-layer vs 6-layer ↓

Cross-comparison analysis

The 4-layer ceiling: a signal-by-signal comparison

The decision to move from 4 to 6 layers is rarely driven by a single signal type. It accumulates across multiple interfaces — DDR, Gigabit Ethernet, USB, analog precision, and power distribution. The table below shows how each signal class performs on a 4-layer board and where it starts to need 6 layers.

DDR3 / DDR4 Memory Bus

800–1600 MHz clock

4-Layer

Data lines route on L1, address/control on L4. Both reference internal GND plane (L2). Clock pair must stay on one layer to avoid via-induced skew. With one signal layer per side, a x16 bus using ~45 traces fills L1 completely, forcing address lines to share L4 with general signals — creating cross-talk risk. DDR3-800 on 4 layers is possible but leaves no margin for layout error. DDR4-1600 on 4 layers is not recommended.

6-Layer

With two dedicated signal layers (L1, L3) and two plane layers (L2 GND, L5 VCC), data and address buses can be separated by layer. L1 carries DQ/DQS + clock (referenced to L2 GND). L3 carries address/command/control (referenced to L4 GND or L5 VCC). L6 handles general-purpose routing. This separation reduces cross-talk by approximately 15–20 dB and provides enough routing channels for DDR4-1600 without via congestion.

Gigabit Ethernet (1000BASE-T)

125 MHz, 4 differential pairs

4-Layer

Four differential pairs (8 traces) plus magnetics routing easily fit on one layer, and 1000BASE-T operates over 4-layer boards successfully. The constraint appears when the PHY is on the opposite side of the board from the RJ45 connector — traces must change layers, crossing plane splits or via anti-pads that degrade common-mode rejection. 4-layer works if the PHY-to-connector route stays on one layer and reference plane continuity is maintained.

6-Layer

A dedicated signal layer (L3 or L6) for all four differential pairs, with a solid reference plane (L4 GND or L5 GND) directly beneath, eliminates the layer-change problem. The additional plane also provides a low-impedance return path for the common-mode currents that generate EMI in Ethernet systems. For 2.5 GbE or automotive Ethernet (1000BASE-T1), 6-layer is strongly preferred.

USB 2.0 / USB 3.0

480 Mbps (2.0) / 5 Gbps (3.0)

4-Layer

USB 2.0 (one differential pair) is comfortable on 4 layers. USB 3.0 adds two SuperSpeed differential pairs (SSTX, SSRX) for a total of 3 differential pairs (6 traces). On a 4-layer board, these must all route on one signal layer (typically L1). When connectors, ESD protection, MUX, and decoupling capacitors are factored in, L1 becomes congested, forcing one of the SuperSpeed pairs to L4 — crossing a via that adds 0.5–1 dB of insertion loss at 2.5 GHz, possibly violating the USB 3.0 −4 dB loss budget.

6-Layer

Distribute the two SuperSpeed pairs across separate signal layers (SSTX on L1, SSRX on L3 or L6) to avoid via transitions entirely. Each pair references a solid GND plane. This keeps insertion loss per pair under −2 dB and preserves the 2 dB margin required by the USB 3.0 specification. The 6-layer stackup also provides a dedicated power island for the USB 3.0 PHY's 3.3 V rail without splitting the main VCC plane.

Mixed-signal: Analog Front-End + Digital Processing

DC – 100 MHz analog bandwidth

4-Layer

On a standard 4-layer stackup (L1 signal, L2 GND, L3 power, L4 signal), the analog section shares L1 with digital traces. The internal GND plane provides some isolation, but digital return currents on L2 induce a voltage gradient across the ground plane that couples into the analog reference. With only one power plane (L3), the analog VCC and digital VCC must share a split plane — the split seam radiates and creates a noise coupling path.

6-Layer

Architecture B (the dual-ground stackup, described below) dedicates L2 and L3 both as ground planes separated by a thin core. This creates a broadband EMI shield between the analog section on L1 and the digital section on L6. The analog ground reference on L2 is undisturbed by digital return currents on L3. L4 becomes the split power plane (analog VCC island + digital VCC island), and L5 provides an additional routing layer for low-speed control signals. ADC SNR improves by 6–12 dB in typical designs.

Power Distribution (3+ Domains)

DC – 10 MHz ripple

4-Layer

With one internal plane (L3) available for power, splitting 3+ voltage domains means the 3.3 V island, 1.8 V island, and 1.2 V island must share the same copper layer. Each split seam is a potential antenna. High-current paths (1.2 V core supply, 5 A or more) require wide copper polygons that are hard to fit when sharing the plane with other domains. The result: IR drop issues and plane congestion that force power routing onto signal layers, consuming routing channels.

6-Layer

Two or even three internal plane layers (L2, L4, L5) can be assigned to power and ground. Common assignment: L2 = GND (solid, no splits), L4 = 3.3 V / 1.8 V split, L5 = 1.2 V core (solid). This arrangement gives each voltage domain its own unbroken plane (or nearly so), reducing IR drop by approximately 50 % compared to a single shared power plane. Decoupling capacitor placement becomes easier because each domain's vias reach its dedicated plane without crossing split seams.

When to upgrade: a decision checklist

☐ Does your design include a DDR3-1066 (or faster) bus with 16 or more data lines?

☐ Do you have 3 or more power domains requiring dedicated plane copper?

☐ Are you routing USB 3.0 and Gigabit Ethernet on the same board?

☐ Does your design include an analog sensor front-end with ≥16-bit ADC resolution sharing a board with digital processing?

☐ Have you already attempted a 4-layer layout and found via congestion or routing channel shortage around the BGA?

☐ Are you targeting automotive, medical, or industrial qualification (IEC 60601, ISO 26262, IEC 61000)?

If 3 or more items are checked, a 6-layer PCB is likely the correct starting point — not an upgrade.

Manufacturing process

Sequential lamination: why 6-layer is not just "4 layers plus two"

A 2-layer board is a single core with copper on both sides. A 4-layer board is a core with prepreg bonded to each side, laminated once. A 6-layer board requires sequential lamination — two separate press cycles with an intermediate etch step. This fundamental process difference affects registration accuracy, material selection, drill strategy, and cost structure.

Core preparation

Two double-sided copper-clad cores are etched: the L3–L4 core (inner layers) and the L2–L5 core (middle pair). Each core is fabricated independently with its own inner-layer imaging, etching, AOI, and oxide treatment. At this stage, L3 and L4 are already defined as copper patterns.

Core A

Core B

↓ First lamination press

First lamination: bond the two cores together

The L2–L3 core and L4–L5 core are pressed together with a prepreg sheet between them (between L3 and L4). Temperature (~180°C), pressure (~350 psi), and dwell time are controlled to ensure complete resin flow, void-free bonding, and correct dielectric thickness between L3 and L4. After lamination, the now-4-layer assembly (L2–L5) is drilled for buried vias if the design uses them, then plated.

Core A

Prepreg

Core B

↓ Second lamination press

Second lamination: bond outer prepreg and copper foil

The assembled L2–L5 sub-stack enters a second press cycle. A prepreg sheet and copper foil are bonded to each side (L1 on top, L6 on bottom). The temperature and pressure profile for the second lamination must be controlled precisely to avoid disturbing the already-bonded L3–L4 interface. After cooling, the full 6-layer stack is drilled (through-holes), electroless copper plated, then outer-layer imaging, pattern plating, and etching follow.

Prepreg

Core A

Prepreg

Core B

Prepreg

Why sequential lamination matters for your design

Registration tolerance: Each lamination cycle introduces a potential shift between layers. A 6-layer board has two registration events (first press + second press), which means the accumulated tolerance between L1 and L6 is wider than between L2 and L5. XFPCB compensates for this in the CAM tooling by adjusting the artwork for each press stage.
Buried via feasibility: Sequential lamination makes buried vias (vias that connect L2–L5 without reaching L1 or L6) possible. They are drilled and plated after the first lamination, then the second lamination encapsulates them. This is a genuine 6-layer advantage (see the via architecture section below).
Copper balance requirement: Each individual core must have balanced copper distribution on both sides before lamination. An unbalanced core can bow during the press, causing the prepreg to flow unevenly and producing a wedge-shaped dielectric (resin-starved on one side, resin-rich on the other). XFPCB reviews copper density per layer pair during CAM.
Material shrinkage: FR-4 shrinks during lamination (typically 0.04–0.08 %). In a two-press process, the L3–L4 core shrinks first, then the outer layers shrink around it. The CAM engineer pre-compensates the artwork for each stage to maintain drill-to-copper registration within ±0.10 mm.

Via technology selection

Six-layer via architecture: matching via type to signal requirement

A 6-layer board supports three via types: through-hole (all layers), buried vias (between inner layers only), and microvias (laser-drilled, typically L1–L2 or L6–L5). Each type has a different cost, impedance impact, and reliability profile. The correct via architecture depends on BGA pitch, signal speed, and board thickness. This section documents the trade-offs.

Through-hole via

Through-Hole Via (PTH)

Default • Lowest cost

The mechanically drilled via that penetrates all six layers. It is the lowest-cost via option and is suitable for nets that connect across the entire stackup or that do not require stubs shorter than the total board thickness.

Drill diameter range 0.20–0.60 mm (mechanical)

Aspect ratio (6-layer 1.6 mm) 8:1–10:1 typical

Stub length Full board thickness (1.2–2.0 mm)

Cost impact Baseline (included in standard fabrication)

When to use: General-purpose signal routing, power distribution, ground stitching, nets that connect more than 3 layers. Avoid for high-frequency signals (>3 GHz) because the via stub acts as a resonant stub filter.

Caution: In a 6-layer board, a through via that connects L1 to L3 creates a 3-layer stub (L4–L6). For signals above 1 GHz, back-drilling the stub can reduce the resonance, but this adds cost. Consider buried vias instead.

Buried via

Buried Via (L2–L5)

6-layer exclusive • Advanced

A via that connects inner layers only (typically L2–L5) and is completely encapsulated within the board. It is drilled and plated after the first lamination (when the L2–L5 sub-stack exists), then the second lamination covers it with the outer prepreg and copper foil. Buried vias are unique to boards with sequential lamination (6+ layers).

Drill diameter range 0.20–0.40 mm (before outer layers)

Stub length Zero (internal only)

Signal integrity Excellent — no stub resonance

Cost impact +15–30% (2 drill + 2 plate cycles)

When to use: High-speed signals that route on inner layers (L3, L4) and must connect to the reference plane (L2, L5) without creating a stub through the outer layers. Also useful for BGA fan-out on inner layers when the outer layers are congested. Buried vias free up routing channels on L1 and L6 because the inner-layer connection does not consume outer-layer pad area.

Process requirement: Buried vias require the designer to specify which layers are connected. Most EDA tools support this in the via definition (e.g., "via from L2 to L5, buried"). XFPCB checks buried via placement against the sequential lamination plan during CAM review — vias must stay within the L2–L5 region and cannot intersect with the outer prepreg boundaries.

Microvia (L1–L2)

Microvia / Laser-Drillled Via

HDI • Fine-pitch BGA

A laser-drilled via that typically connects L1 to L2 (or L6 to L5) through the outer prepreg only. In a 6-layer board, microvias are useful when fanning out from a fine-pitch BGA (pitch ≤ 0.65 mm) where through vias would be too large to fit between adjacent pads. Microvias are not standard for 6-layer boards but can be added as an HDI option.

Drill diameter range 0.075–0.150 mm (laser)

Via-in-pad capable Yes (with conductive fill + cap plating)

Signal integrity Excellent — very low inductance

Cost impact +40–60% (laser drill + fill process)

When to use: Designs that combine 6-layer routing density with fine-pitch BGAs (0.5–0.65 mm pitch), where through vias cannot fit between BGA pads. Also useful for very thin boards (<1.0 mm) where mechanical drilling at small diameters approaches the aspect ratio limit. Microvias in a 6-layer board are typically part of a 6+N+6 HDI structure, where the outer layers use microvias and the inner layers use through vias.

Design note: Microvias require a via-in-pad or via-in-pad-with-fill approach for BGA fan-out. If the microvia is not filled, solder will wick into the via during reflow, causing a head-in-pillow defect. XFPCB offers copper-filled and conductive-epoxy-filled microvias for reliable via-in-pad assembly.

Stackup architecture

Three 6-layer stackup architectures: what each one is good for

There is no single "standard" 6-layer stackup. The optimal layer arrangement depends on the number of high-speed signals, the power domain count, the need for analog isolation, and the board thickness. Below are three proven architectures that represent different trade-offs between signal integrity, power distribution, and cost.

Architecture 1 Signal – GND – Signal – GND – Signal – GND Most common • Best SI ▼

L1 — Signal / Components

Prepreg — 0.10–0.20 mm

L2 — Ground Plane (solid, no splits)

Core — 0.25–0.50 mm

L3 — Signal / High-speed traces

Prepreg — 0.20–0.40 mm

L4 — Ground Plane (solid)

Core — 0.25–0.50 mm

L5 — Signal / Power routing

Prepreg — 0.10–0.20 mm

L6 — Ground Plane (solid, secondary components)

Board thickness target 1.2–1.6 mm

Signal layers with GND reference 3 (L1, L3, L5 all reference an adjacent GND plane)

Power planes None dedicated — power distributed via polygons on L5 or L3

Impedance control Excellent on all three signal layers

Cost index Baseline (1.0×)

Strengths

Every signal layer has an adjacent ground plane — the ideal arrangement for controlled impedance and return current management.
L2 and L4 provide inter-plane capacitance for high-frequency decoupling (~200–500 pF for a typical 100×80 mm board).
Best architecture for mixed-signal designs when analog and digital signals can be assigned to different signal layers.

Limitations

No dedicated power plane — power routing on signal layers consumes routing channels and requires wider traces for current >1 A.
If multiple power domains are needed, L5 must carry split power polygons, which reduces its effectiveness as a routing layer.
Board thickness may exceed 1.6 mm if thick cores are used, requiring longer drill cycles.

Best for: Designs with 2–3 power domains, digital-heavy routing with DDR / GbE / USB, and where SI performance is the primary requirement. This is XFPCB's recommended default for most 6-layer boards.

Architecture 2 Signal – GND – GND – Signal – Power – Signal Power-rich • Mixed-signal ▼

L1 — Signal / Components (analog + digital)

Prepreg — 0.10–0.15 mm (thin)

L2 — Ground Plane (solid, analog reference)

Core — 0.10–0.20 mm (thin, broadband isolation)

L3 — Ground Plane (solid, digital reference)

Prepreg — 0.20–0.40 mm

L4 — Signal / Control / Low-speed

Core — 0.50–0.71 mm

L5 — Power Plane (split: analog VCC, 3.3 V, 1.8 V)

Prepreg — 0.10–0.20 mm

L6 — Signal / Secondary components

Board thickness target 1.0–1.6 mm

Signal layers 3 (L1, L4, L6)

Plane layers 3 (L2 GND, L3 GND, L5 Power split)

Isolation Excellent — dual GND planes create broadband EMI shield

Cost index 1.15–1.25× (thin core + dual plane complexity)

Strengths

Dual ground planes (L2, L3) with thin dielectric between them create a parallel-plate capacitor with >500 pF distributed decoupling — excellent for suppressing GHz-range noise.
Dedicated power plane (L5) can accommodate 3–4 split voltage domains without compromising signal-layer routing.
L1 signal layer has a thin prepreg to L2, providing a very tight reference plane for low-impedance microstrip routing (good for RF front-ends).

Limitations

L4 is a stripline layer between two planes — impedance is lower and trace widths must be wider for the same target, consuming more routing space.
Thin core between L2 and L3 (0.10–0.20 mm) can be difficult to source for very large panel formats (>350 mm).
Additional lamination complexity: the thin core may require a controlled low-flow prepreg to prevent resin starvation.

Best for: Mixed-signal designs with sensitive analog front-ends (16+ bit ADC, precision DAC, audio codecs), designs combining RF (≤3 GHz) with digital processing, and medical or instrumentation equipment requiring low noise floors.

Architecture 3 Signal – GND – Signal – Signal – GND – Signal Routing-dense • Cost-sensitive ▼

L1 — Signal / Components

Prepreg — 0.10–0.20 mm

L2 — Ground Plane

Core — 0.50–0.71 mm

L3 — Signal / High-speed or dense routing

Prepreg — 0.71–1.27 mm (thick)

L4 — Signal / Power routing or additional traces

Core — 0.50–0.71 mm

L5 — Ground or Power Plane

Prepreg — 0.10–0.20 mm

L6 — Signal / Secondary components

Board thickness target 1.6–2.0 mm

Signal layers with GND reference 3 (L1 over L2, L3 over L2 or L5, L6 over L5)

Blind inner routing L3 and L4 can route densely with via freedom

Routing density Highest of the three architectures

Cost index 0.95–1.05× (no thin cores, simple press)

Strengths

Two adjacent inner signal layers (L3, L4) with no plane between them — ideal for short, high-density routing where via congestion is the main problem.
Simpler lamination: the thick prepreg between L3 and L4 reduces registration sensitivity, making it the most forgiving 6-layer stackup for manufacturing.
Lower cost than Architecture 1 or 2 because no thin cores are needed and the prepreg stack is standard.

Limitations

L3 and L4 are not adjacent to a reference plane — signals between them cannot be impedance-controlled on that segment (must rely on L2 or L5 reference through vias).
The thick prepreg between L3 and L4 means the reference plane distance for L3 (to L2) and L4 (to L5) is different, making impedance matching between layers harder.
Not suitable for designs that require 3+ clean reference planes for simultaneous high-speed interfaces.

Best for: Routing-dense designs where the primary constraint is trace congestion, not signal integrity — for example, large FPGA boards with many low-speed I/Os, complex power management boards, or multi-channel data acquisition systems with moderate clock speeds (≤200 MHz).

Quick architecture selector

Primary constraint is signal integrity (DDR, GbE, USB 3.0, >3 power domains)? → Architecture 1 (three ground-reference pairs)

Mixed analog + digital with sensitive ADC/DAC or RF front-end? → Architecture 2 (dual ground + dedicated power plane)

Primary constraint is routing density (more traces per mm² needed)? → Architecture 3 (two adjacent inner routing layers)

Design for Manufacturing

Six DFM rules specific to 6-layer PCBs

Many DFM checklists are generic across all layer counts. The six items below are specific to 6-layer boards — they arise from the sequential lamination process, the via structure, and the accumulated registration tolerances that a 2-layer or 4-layer board simply does not have.

Layer-to-layer registration: the two-press penalty

Each lamination cycle introduces a potential offset between the layers bonded in that cycle. In a 6-layer board, L1 is registered during the second press against L2, which was already registered during the first press against L3/4/5. The cumulative tolerance between L1 and L6 is approximately ±0.15 mm (vs ±0.08 mm for a 4-layer board's outer-to-inner registration). This affects annular ring requirements: a via pad that connects L1 to L6 must have a larger pad diameter on L1 and L6 than on inner layers.

DO Specify 0.15 mm minimum annular ring on L1 and L6 (outer layers), 0.10 mm on inner layers (L2–L5) for any via that connects through the full stack.

DON'T Use the same pad diameter for all layers on a through via. XFPCB's CAM system adjusts this automatically if the design file uses uniform pad sizes, but not all EDA tools export per-layer pad dimensions correctly.

Copper balance per core pair

In a 6-layer board, the two internal cores (L2–L3 and L4–L5) are etched and pressed independently before the final lamination. If L2 has 70% copper density and L3 has 20%, the L2–L3 core will bow during the first press, causing uneven resin flow in the prepreg on one side. This produces a wedge-shaped dielectric that shifts the impedance of traces on L3 by up to ±15% across the panel — a common root cause of impedance test failures that are mistakenly attributed to etching variation.

DO Aim for copper density within 15 percentage points between the two sides of each core pair (L2 vs L3, L4 vs L5). Use cross-hatch ground pour or copper thieving to balance asymmetric areas.

DON'T Rely on the outer layers (L1, L6) to balance the copper distribution — they are added in the second press and cannot correct a bowed core from the first press.

Buried via capture pad clearance

If the design uses buried vias (L2–L5), the capture pad on the outer prepreg interface (L2, L5) must be sized to accommodate both the first-press registration tolerance and the second-press registration tolerance. A buried via drilled after the first press is centred on the L2–L5 sub-stack. When the outer prepreg and copper foil are added in the second press, the L1-to-L2 registration tolerance can shift the outer pad relative to the buried via barrel.

DO Use a minimum capture pad diameter of 0.55 mm for buried vias on the interface layers (L2 and L5) when using a 0.25 mm finished hole size. This provides ±0.15 mm registration margin.

DON'T Stack buried vias directly above through vias in the same location — the two-stage drill can create a resin-rich zone that traps air or causes CAF (conductive anodic filament) growth over time.

Resin flow and glass style selection for the centre prepreg

In a 6-layer stackup, the centre prepreg (between L3 and L4 in most architectures) is the thickest dielectric layer in the board. Its resin content and glass weave style (106, 1080, 2116, 7628) directly affect the dielectric thickness between the inner signal layers and their reference planes. A 7628 glass style has higher glass-to-resin ratio, which means less resin available to fill gaps around buried vias — potentially creating voids.

DO Specify 2116 or 1080 glass style for the centre prepreg when the design uses buried vias, to ensure sufficient resin volume for void-free encapsulation. Use 7628 only for non-via-heavy designs with thick dielectric requirements.

DON'T Assume the centre prepreg thickness in your EDA impedance calculator will match the fabricated value — the actual pressed thickness depends on resin fill around via barrels and copper features on adjacent layers. XFPCB provides actual pressed thickness values from coupon cross-sections.

Plated through-hole barrel reliability across two laminations

A through-hole via in a 6-layer board must survive two thermal cycles (the second lamination press after the barrel is plated) plus the assembly reflow cycles. The thermal expansion of the core materials at the L3–L4 interface creates z-axis stress that can crack the copper barrel. This is especially relevant for thick boards (≥1.6 mm) and high-Tg materials.

DO Use TG170 or higher material for 6-layer boards with through vias that carry current >1 A or that must survive ≥3 reflow cycles. The lower z-axis CTE of TG170 (35–50 ppm/°C vs TG135's 50–70 ppm/°C) significantly reduces barrel stress.

DON'T Use minimum copper plating thickness (typically 20–25 µm) in the barrel for 6-layer boards with aspect ratios above 8:1. Specify 30–35 µm minimum barrel copper for high-reliability applications.

Impedance coupon placement for multi-stage process control

In a 6-layer board, there are three distinct dielectric interfaces that determine impedance: L1-to-L2 (microstrip), L3-to-L2 or L3-to-L4 (stripline), and L6-to-L5 (microstrip). Each interface is pressed at a different stage (L1/L6 in the second press, L3–L4 in the first press) and may have different dielectric thicknesses. A single impedance coupon at the panel edge cannot represent all three interfaces accurately.

DO Request 2–3 impedance coupons per panel when different impedance targets exist on different layer pairs. For example: coupon A for L1–L2 microstrip targets, coupon B for L3–L4 stripline targets, coupon C for L6–L5 microstrip targets.

DON'T Expect a single coupon to validate impedance on all signal layers. XFPCB's standard practice is to place one coupon per impedance set; if the RFQ specifies multiple impedance targets, we include the corresponding coupons and measure each separately.

These six DFM rules are applied during XFPCB's CAM review for every 6-layer PCB order. We send a DFM report before production begins — not after the boards are built. Send your files for a 6-layer DFM review.

Specification reference

6-Layer PCB engineering capabilities at XFPCB

Each specification below is annotated with the engineering implication — what the number means for your design, not just what it is.

Layer structure

Layer count: 6 copper layers (2 outer + 4 inner)
Lamination type: Sequential (2 press cycles) — enables buried vias but requires tighter registration management
Core structure: 2 internal cores (L2–L3, L4–L5) + 2 outer prepreg layers (L1, L6)

Materials

FR-4 (standard): Tg 130–140°C, Dk 4.2–4.5 at 1 GHz. Suitable for general-purpose 6-layer designs without high thermal or RF requirements.
High-Tg FR-4: Tg 170–180°C, Dk 4.1–4.4. Recommended default for 6-layer — lower z-axis CTE reduces via barrel stress across two lamination cycles.
Rogers / Hybrid: RO4003C (Dk 3.38), RO4350B (Dk 3.48). Available as full-stack or hybrid (Rogers core + FR-4 prepreg) for cost-optimised RF performance.

Physical dimensions

Board thickness: 0.8–2.0 mm standard. 0.6–3.2 mm available. Thickness selection affects via aspect ratio and mechanical stiffness.
Panel size (max): 600 × 500 mm (standard). Larger sizes available on request. Sequential lamination limits maximum panel size when thin cores (<0.15 mm) are used.
Copper weight: 0.5 oz to 3 oz outer / 0.5 oz to 2 oz inner. Heavier copper on inner layers increases the minimum dielectric spacing and affects impedance calculation.

Via technology

Through via (PTH): Min drill 0.20 mm, aspect ratio up to 10:1. Standard for most 6-layer designs. Back-drilling available for >1 GHz signal stubs.
Buried via: Available for L2–L5 connections. Requires sequential lamination. Recommended for high-speed signals that need stub-free transitions between inner layers.
Microvia (HDI): Available as 1+N+1 structure. Laser-drilled 0.075–0.150 mm. Conductive fill available for via-in-pad BGA fan-out.

Impedance control

Tolerance (standard): ±10%. Verified via TDR measurement of production panel coupons.
Tolerance (tight): ±8% or ±5%. Requires pre-production test panel and coupon verification per impedance set.
Common targets: 50 Ω SE, 90 Ω diff (USB), 100 Ω diff (Ethernet), 85 Ω diff (PCIe). Multiple target sets supported on one stackup.

Quality & testing

AOI: 100% automated optical inspection on all layers (inner + outer). Post-lamination AOI available for sequential press verification.
Electrical test: Flying probe or fixture. Opens and shorts verification on all nets. Impedance TDR verification on request.
Microsection analysis: Available for cross-section verification of via barrel plating thickness, dielectric thickness, and layer registration accuracy.

Need a specification not listed here? Send your requirements and XFPCB will confirm capability before quoting.

Start your engineering consultation

Send your 6-layer PCB requirements for engineering review

A 6-layer PCB quotation is not a simple area-times-price calculation. The stackup architecture, via strategy, material selection, impedance targets, and test plan all affect the manufacturing process and cost. XFPCB's engineering team reviews each submission and responds with a structured quotation that includes:

Stackup architecture recommendation based on your signal types and density
Material selection with TG, Dk, and Df values matched to your operating conditions
Impedance control plan with target trace geometries and coupon placement
Via strategy recommendation (through, buried, or microvia) based on BGA pitch and signal speed
DFM report identifying layer registration, copper balance, and resin flow considerations
Lead time and pricing for prototype and production quantities

For the fastest engineering reply, include Gerber files, drill files, a layer stackup drawing or description, target impedance values if applicable, material preferences, quantity, and delivery country.

"The DFM report XFPCB sent before our first 6-layer order caught a copper balance issue on our inner core that would have caused a 2-week delay. They adjusted the stackup and the boards came back within impedance tolerance on all layers."

— Hardware engineering manager, industrial automation company, Germany

When 4 layers stop being enough: the 6-layer signal integrity threshold

The 4-layer ceiling: a signal-by-signal comparison

DDR3 / DDR4 Memory Bus

Gigabit Ethernet (1000BASE-T)

USB 2.0 / USB 3.0

Mixed-signal: Analog Front-End + Digital Processing

Power Distribution (3+ Domains)

When to upgrade: a decision checklist

Sequential lamination: why 6-layer is not just "4 layers plus two"

Core preparation

First lamination: bond the two cores together

Second lamination: bond outer prepreg and copper foil

Why sequential lamination matters for your design

Six-layer via architecture: matching via type to signal requirement

Through-Hole Via (PTH)

Buried Via (L2–L5)

Microvia / Laser-Drillled Via

Three 6-layer stackup architectures: what each one is good for

Strengths

Limitations

Strengths

Limitations

Strengths

Limitations

Quick architecture selector

Six DFM rules specific to 6-layer PCBs

Layer-to-layer registration: the two-press penalty

Copper balance per core pair

Buried via capture pad clearance

Resin flow and glass style selection for the centre prepreg

Plated through-hole barrel reliability across two laminations

Impedance coupon placement for multi-stage process control

6-Layer PCB engineering capabilities at XFPCB

Layer structure

Materials

Physical dimensions

Via technology

Impedance control

Quality & testing

Send your 6-layer PCB requirements for engineering review

Choose the right layer count before you submit your RFQ

PCB Manufacturing

PCB Assembly

Capabilities

Industries

Company & Support