Most early SMT defects blamed on "the factory" start as footprint or package mistakes in CAD. A resistor value can be perfect in the schematic while the land pattern is for the wrong EIA size, the diode polarity mark is missing, or the courtyard collides with a tall connector.
This guide walks common PCB parts through a DFM lens used in overseas quoting: electrical role matters, but package code, land pattern, and process path decide whether the board assembles.
Passives that look simple until reflow
Resistors set current and bias; watch power rating and package thermal limits, not only ohms. Capacitors filter and decouple - ceramic vs electrolytic vs tantalum change ESR, polarity, and height. Inductors store magnetic energy for regulators and EMI; core type and shielding affect neighbors.
Group passives by package family (0402, 0603, electrolytic can, etc.) in the BOM review so stencil aperture and nozzle strategies stay coherent.
Actives and semiconductors
Diodes, transistors, and ICs define behavior. Package choice (SOD, SOT, SOIC, QFN, BGA) drives pad geometry, thermal vias, and inspection method. Crystal packages add mechanical fragility and keep-out needs. Photodiodes, thermistors, and similar stimulus-sensitive parts need placement rules that pure digital parts do not.
Polarity and pin-1 marking on silkscreen and assembly drawings prevent systematic reverse stuffing that AOI may catch late.
Electromechanical parts
Connectors, switches, relays, and buzzers introduce mechanical stress, hole size, and solder-fill requirements. Press-fit, wave, or selective solder may be mandatory. Mounting holes and standoffs need copper keep-outs. Shield cans need reliable solderable footprints.
Structures that are not BOM lines but still fail builds
Footprints must match the exact package drawing (IPC-7351 style discipline helps). Vias connect layers - via-in-pad under BGAs needs fill/plate plans. Solder mask clearance on fine pitch prevents bridging. Silkscreen that lands on pads creates assembly defects and inspection noise.
Signal and thermal side effects of part choice
High-speed packages force controlled impedance and short escapes. Power packages force copper and thermal vias. Crowding heat sources next to electrolytics or crystals creates field failures that look mysterious in firmware.
DFM habits that cut respins
Lock package MPNs and footprints before layout freeze. Run courtyard and polarity checks. Confirm the quoted SMT line can place the smallest and tallest parts on the BOM. Add test points where service needs them. Avoid inventing land patterns when manufacturer recommended patterns exist.
For package-dense designs see BGA and CSP packages guide and SMD IC package types. Send BOM-plus-footprint packages through how to place an order.