The Gerber package cleared every DRC rule the layout team had loaded. Trace width, clearance, drill-to-copper -- all green. Three days later CAM emailed an engineering query: annular rings on two via nets sat under the fab's Class 2 process window after drill tolerance, and a cluster of acute T-junctions would trap etchant on the outer layers. The spin waited while the designer thickened pads and cleaned routes. That delay is the gap this article is about: DRC proves the layout matches the rules you typed into the EDA tool. DFM asks whether a real China fab process sheet can etch, drill, plate, mask, and assemble the board at yield.
Layout engineers who pass DRC then absorb CAM EQs, and buyers who want cost down without seeing where manufacturability hides the money, both land here. The fix is not another checkbox pass at release. It is designing against fabrication and assembly capability from the start -- Design for Fabrication plus Design for Assembly -- so the first quote is buildable and the first panels are not a surprise.
DFM as matching a China fab process sheet
Design for Manufacturing on PCBs means aligning geometry, materials, and tolerances with what a specific factory can actually run -- not with an idealized CAD grid. In shop language that is DFF (bare-board fabrication: etch, drill, plate, mask) joined with DFA (assembly: paste, placement, reflow, inspection). Together they are DFMA. DRC never sees solder paste release, drill wander, etch undercut, or how HASL topography affects a 0402 during reflow. Those live on the process sheet and in the EQ inbox.
A China fab process sheet lists minimum trace/space by copper weight, drill sizes and aspect-ratio limits, annular-ring targets by IPC class, solder-mask dam resolution, and finish options. Programming those numbers into your design rules before routing is DFM work. Running only the EDA default rule deck is hoping the fab's window matches your library. Wells-style assembly DFM makes the same point from the other end: manufacturability starts at schematic and floor planning, not as a filter after Gerbers are zipped. The general industry 1-10-100 heuristic (often called the Rule of Ten) says a defect costs roughly an order of magnitude more to fix at each stage it survives -- layout, prototype, production, field. That is a general industry heuristic, not an XFPCB price quote; it is why a CAM EQ at quote time is cheaper than a respin after assembly.
DRC remains necessary. It is not sufficient. Via-in-pad without a fill note, mask dams too thin for the fab's LPI resolution, acid-trap corners, and asymmetric pads on tiny passives all pass many DRC decks and still stop or scrap boards. JLCPCB-class verification guidance calls out acid traps, copper/mask slivers, and insufficient mask dams as classic DFM catches that standard DRC misses -- the same issues China CAM engineers flag when they protect yield.
IPC class choices that quietly inflate cost
IPC-2221C is the current generic printed-board design backbone (revision C, December 2023), with companions such as IPC-6012 for rigid performance/acceptance and IPC-A-600 for visual criteria. Product class is the lever buyers misuse most often:
Class 1 covers general electronics. Class 2 covers dedicated service electronics. Class 3 covers high-reliability product. Class drives annular-ring minimums, acceptance criteria, and how much process margin the fab must hold. Calling Class 3 on a commercial IoT board when Class 2 matches the field risk raises plating, inspection, and scrap cost without buying field reliability you will measure. Under-calling Class 3 on a life-critical or harsh-duty board trades short-term quote dollars for field failures. Put the real reliability need on the RFQ in plain language, then pick the class that matches -- not the highest number that sounds safe.
Trace-width charts from older IPC-2221 eras still circulate in online calculators; current work should follow IPC-2152 for current-carrying capacity and the fab's copper-weight capability table. Over-specifying 0.5 oz fine line everywhere when 1 oz with slightly wider traces meets current and yield is another quiet cost adder. Under-specifying copper for continuous load is a field heater. Match class, copper, and spacing to the product environment the same way you match layer count.
Where green DRC still fails on the line
Annular ring is the copper donut around a drilled hole. Drill position tolerance eats designed ring; too little left and you get breakout or opens. Rule-of-thumb industry guidance often cites more than about 3.5 mil per side on vias and about 6 mil on through-hole pins, then verifies against the fab sheet and IPC class. Designing to the minimum your EDA allows without the fab's drill tolerance is how a green DRC becomes a red EQ.
Aspect ratio -- board thickness divided by drill diameter -- governs whether plating solution reaches the barrel center. Industry practice commonly keeps through-hole aspect ratio at or below about 10:1 for standard plating reliability (some assemblers prefer staying near 8:1). A thick board with tiny drills that "fit" electrically can still plate thin in the middle and fail under thermal cycle. That failure mode is invisible to a clearance-only DRC.
Acid traps are acute copper angles under 90 degrees where etchant pools and over-etches. Autorouters still produce them; DRC that only checks width/spacing will not rename a sharp inside corner. Route at 45 or 90 degrees and clean jogs before release. Slivers -- narrow isolated copper or mask wedges -- peel and float, creating intermittent shorts. Mask dams between fine-pitch pads need enough width for the fab's mask process (industry talk often lands near 4 mil / 0.1 mm minimum); dams that DRC never measured become solder bridges in reflow. JLCPCB verification write-ups treat these etch and mask issues as the bridge between CAD and factory yield for a reason.
Tombstoning lifts one end of a small passive (0402, 0201) when pad wetting or heat is unequal. Symmetrical pads, matched trace necks, consistent orientation, and thermal relief when one pad ties to a pour all reduce the risk. Surface finish matters here too: industry commentary often notes HASL can raise tombstone incidence roughly several times versus flatter ENIG on tiny parts -- again a process observation, not a site-specific XFPCB guarantee. DFA shows up in orientation consistency and pad balance as clearly as DFF shows up in etch geometry.
These modes show up as CAM questions, yield hits, or assembly scrap. They are why "DRC clean" and "fab ready" are different sentences.
Finish, copper, and file format as cost levers
HASL is usually the lower-cost, durable finish and works for many through-hole and coarser SMT jobs. Its uneven surface fights fine-pitch BGAs, QFNs, and sub-0.5 mm pitch lands. ENIG costs more per area in general industry heuristics (often cited on the order of a few tenths of a dollar per square inch of premium versus HASL -- treat that as a market heuristic, not an XFPCB quote) but gives a flat, coplanar pad that assembly can trust on fine pitch. Choosing HASL to "save finish money" on a BGA board often spends more on EQ churn, stencil tuning, and scrap.
Copper weight sets etch compensation and minimum space. Heavier copper needs wider gaps for the same yield. Layer count and board size lock most fab cost before routing aesthetics matter. File format is the quiet lever: bare Gerber forces CAM to infer stackup and intent; Gerber X2, ODB++, or IPC-2581 carry more manufacturing context and cut guesswork. Send the most intelligent format your fab accepts, with a readable stackup table and fab notes that state class, finish, impedance, and via-fill requirements in text CAM can quote against.
A package CAM can quote without guessing
A DFM-ready package lets CAM price and schedule without inventing your intent. Include copper layers, masks, silkscreen, paste layers when assembly is in scope, board outline, and NC drill with a tool list. Add a stackup table (dielectric, copper weight, target impedance if any). State IPC class, surface finish, via treatment (tented, plugged, filled and capped when via-in-pad exists), and any controlled-impedance coupons. For PCBA, resolve the BOM -- no TBD lines -- and send a centroid file with rotation and side. Call out panelization preferences or accept the fab's recommendation in writing so depaneling stress is not a surprise at the edge of ceramic capacitors.
When you upload, expect EQs on features that sit on the edge of the process window. Answer them against the process sheet, not against "it passed DRC." If annular ring, aspect ratio, or mask dam capability forces a change, change the layout before the PO -- that is the cheap move under the 1-10-100 heuristic.
Early fab conversation is the cheapest respin insurance. Share the process sheet targets while the stackup and via strategy are still soft. Ask whether Class 2 annular rings, your drill sizes, and your finest pitch fit standard process or need advanced pricing. Bring finish and copper weight into that same call so buyers are not optimizing the wrong line item. XFPCB CAM reviews packages against real China fab capability so layout teams get EQs while copper is still editable -- not after a green DRC screenshot has already locked a bad spin.