Functional Circuit Testing: When to Power On, DFT & RFQ

Factory playbook for powered FCT: when to power on after AOI/X-ray/flying-probe-or-ICT, volume gate from bench to reusable nest to custom fixture, what FCT catches that structural tests miss, what it does not replace, DFT for power/debug/fixture/golden-board, and China fab/EMS RFQ checklist (pass/fail, firmware rev, fixture ownership, cycle class, data logs).

Last updated
Functional circuit testing gate: when to power on, DFT for fixtures, RFQ checklist

Functional circuit testing (FCT) is the powered gate that asks whether the assembled board behaves like the product — rails come up, firmware boots, interfaces talk, and defined loads stay inside limits. It is not AOI or X-ray (those are visual/structural solder and placement checks). It is not flying probe or bed-of-nails ICT (those are unpowered or limited structural-electrical checks for opens, shorts, and accessible passives). This playbook is the when to power on, DFT for fixtures, and RFQ side for China fab/EMS buyers: volume gate from bench to custom fixture, what FCT catches that structural tests miss, what it must never replace, and how to write comparable quotes. It does not rewrite flying-probe method selection, FQC/packaging outbound gates, first-article lot hold, or turnkey-vs-consignment kit ownership.

Functional circuit testing gate: when to power on, DFT for fixtures, RFQ checklist

Quick answer: when to power the board on

Power on for FCT after the structural and cosmetic gates you named for that revision have already cleared — typically AOI (and X-ray where BTCs/BGAs need it), a named electrical method if you use one (flying probe, ICT, or equivalent), and any first-piece setup release the PO requires. Then run a revision-locked procedure: known firmware image, defined stimulus, measurable pass/fail limits, and a written stop rule when a board fails. Prefer manual/bench FCT on prototypes and early NPI. Prefer a reusable fixture and script when the layout is mostly frozen but volume is still low. Prefer a custom fixture + automated scripts when cycle time, operator skill, and lot size make hand probing the bottleneck. Never treat “FCT included” as a substitute for bare-board electrical test, SMT cosmetic AOI, or hidden-joint X-ray.

GateWhat it answersTypical stageDoes not own
AOIVisible solder, placement, polarity cuesAfter SMT / selectiveHidden BTC joints; power-on behavior
X-rayVoids, bridges, opens under BGA/QFNSample or 100% on BTC riskFirmware, protocol, rail sequencing
Flying probe / ICTOpens/shorts; accessible R/C/polarityBare board and/or PCBAFull powered product behavior
FCTPowered end-use (or defined subset)After structural gatesSMT cosmetics; bare-board netlist alone
FQC / packingFinished appearance + outbound packEnd of lineMethod-level electrical or FCT depth
FAI / first-pieceProduction setup release for the lotBefore remaining PCBA lotOngoing 100% FCT definition by itself

Volume gate: bench → reusable setup → custom fixture

FCT cost is mostly procedure clarity, fixture NRE, and cycle time — not a mysterious “test tax” line. Match the hardware to volume and layout stability:

Prototype / EVT bench. Engineer or technician runs a written checklist: lab PSU with current limit, debug header or bootloader cable, scope/DMM on named rails, host PC for UART/USB/CAN as needed. Strengths: same-day changes when firmware or limits move. Weaknesses: operator-dependent timing, weak data logs, hard to compare quotes across houses. Use this when the schematic is still churning and a nail plate would be scrap.

Low-volume reusable setup. A simple nest, pogo block, or clamp fixture that lands on dedicated power and sense points, plus a scripted sequence (Python, LabVIEW, vendor runner — the tool matters less than revision control). Strengths: repeatable stimulus, basic logging, trainable operators. Weaknesses: still slower than a purpose-built bed; connector life and alignment need a maintenance note. Use this when the PCB outline and test-point map are stable enough to amortize a light fixture but monthly volume does not justify a full ICT-style plate.

Volume custom fixture + scripts. Dedicated nest, guided connectors, barcode/rev read, automated power sequencing, and pass/fail UI tied to MES or a traveler. Strengths: predictable cycle time, less skilled labor variance, audit-friendly logs. Weaknesses: NRE, lead time, and painful rework when you move a connector or test point after freeze. Use this when the PO defines a cycle-time class and the layout is under change control.

Write the RFQ with the class you want quoted (bench procedure only / reusable nest / custom automated). Leaving “functional test” unqualified invites one bidder to price a five-minute bench check and another to price a PLC fixture — numbers that look cheap or expensive for the wrong reason.

What FCT catches that structural tests miss

Structural electrical tests prove connectivity and many passive values. Powered FCT proves behavior under energy and software. Typical escapes that only show up after power-on:

  • Firmware and boot path. Wrong image, failed flash, brown-out during boot, missing boot config bits, or a part that nets correctly but never leaves reset. Flying probe does not execute code.
  • Protocol and interface bring-up. USB enumeration, UART handshake, I²C/SPI device ACK, Ethernet link, CAN bus traffic, RF association — anything that needs clocks, stacks, and a peer. Continuity to a connector pin is not the same as a clean packet.
  • Wrong value that still nets. A resistor in tolerance for the ICT band but wrong for the regulator soft-start; a capacitor that passes a crude C check yet starves a PLL; a crystal that solders fine and still will not oscillate under the intended load caps. FCT with named limits catches these when the procedure measures the rail, frequency, or register that matters.
  • Intermittent connector and seating. Partial mate, bent pin that still “touches,” flex-tail strain, or a header that AOI saw as present but that fails under slight cable pull or thermal soak. A short powered exercise with wiggle or defined mate force is often the first honest signal.
  • Sequencing and protection. Inrush, rail order, UVLO/OVP trips, and load-step recovery. Unpowered nets can look perfect while the product brown-outs every cold start.

Document each of these as a named step with a limit in the FCT procedure. “Board powers on” is not a criterion — “3V3 within X–Y after Z ms, current below Imax, USB enumerates as VID/PID …” is.

What FCT does NOT replace

Buyers sometimes collapse every inspection word into “test.” That creates escapes and argumentative NCRs. Keep these boundaries hard:

  • AOI for SMT cosmetics. Tombstones, insufficient fillet on exposed joints, wrong polarity visible from above, missing chip parts — FCT may pass with a partially starved rail or fail for unrelated reasons. Optical process control stays on AOI (and SPI where you use it).
  • X-ray for BGA / BTC voids and hidden bridges. A ball field can have a marginal joint that still limps through a light FCT and dies in the field. If your risk model needs void % or bridge screening under packages, specify X-ray sample or 100% separately.
  • Bare-board electrical test. Opens and shorts in the bare interconnect belong to a named bare-board method (flying probe, fixture ET, or equivalent) before you invest assembly and FCT time. FCT is a poor, expensive netlist checker.
  • FQC appearance and packing. Cosmetics of the finished unit, label correctness, and moisture/ESD outbound stack are final-gate / packaging language — not FCT depth.
  • FAI lot-hold. First-article inspection releases the production setup (stencil, feeders, programs, reflow, coat if applicable) before the remaining lot. An FCT pass on one board is evidence you may attach to FAI; it is not the whole FAI definition.
  • Turnkey vs consignment ownership. Who buys the fixture, golden board, and spare pogos is a commercial line. Do not bury it inside a vague “FCT included” phrase.

If a defect class has another named gate, keep FCT focused on powered behavior so quotes and failure analysis stay honest.

DFT for FCT — power, access, and fixture geometry

Design-for-test for FCT is mostly about safe power injection, stable contact, and programming access — different from flying-probe pad grids, though some lands serve both. Confirm mechanical details with the EMS that will build the fixture; treat the list below as RFQ conversation starters, not a universal plant capability claim.

Practical DFT habits:

  • Power and return test points. Dedicated lands or connectors for input power and solid returns, sized for the fixture current you intend. Avoid powering only through fragile production connectors you do not want to wear out in test.
  • Sense / measure points. Bring out rails, key clocks, and interface sense nets to pads or a debug header so the fixture (or bench) can measure without scraping solder mask or probing fine-pitch pins.
  • Programming and debug headers. Bootloader, JTAG/SWD, UART, or vendor ISP pads with clear pinout on the assembly drawing. Lock the firmware revision that FCT must load or verify — a Rev A binary on a Rev B BOM is a classic false-fail generator.
  • Fixture fiducials and outline. Mechanical datums, tooling holes, and keep-outs for clamps so the nest repeats. Tall shields, batteries, and displays need clearance notes or a two-step mate sequence.
  • Connector mate strategy. Specify which production connectors the fixture may cycle, mating cycles allowed, and whether a sacrificial test connector or pogo interface is preferred.
  • Safety and protection. Current-limit expectations, reverse-power diodes if relevant, and “do not probe” high-energy zones. FCT should not be the first time a shorted board meets an unlimited bench supply.
  • Golden-board criteria. Define what makes a reference unit: same fab/assembly rev, known-good FCT log, and storage/handling rules. Golden boards drift; write a recalibration or re-verification interval in the procedure instead of assuming one forever unit.
DFT for functional circuit testing: power points, debug headers, fixture fiducials, golden board

If a net or interface cannot be exercised in FCT, list it as an exclusion with the mitigation (boundary scan, system-level test later, sample X-ray) rather than implying 100% product coverage from a partial script.

Pass/fail, firmware rev, and data you keep

Comparable FCT quotes need the same definition of done:

  1. Pass/fail criteria — numeric limits per step (voltage, current, frequency, message ID, sensor reading). Attach the procedure PDF/rev, not a chat summary.
  2. Firmware / FPGA image — hash or version string, who flashes (EMS vs buyer), and whether blank-check / verify is required after program.
  3. Stimulus and load — dummy loads, loopback plugs, RF attenuators, or peer devices that must be present. Missing fixtures are the usual “it worked on our bench” dispute.
  4. Environmental notes — ambient only vs short thermal soak; ESD posture; whether conformal coat is already applied (coat changes access and leakage).
  5. Data logs — what gets stored (serial, step results, fail code), retention period, and whether a fail board ships with a traveler note or is held.
  6. Retest rule — one reflash allowed? Connector reseat allowed? Who authorizes a second FCT after rework?

Without those six, two China houses are not bidding the same powered gate.

RFQ checklist for comparable China fab / EMS quotes

Put the same bullets in every FCT RFQ:

  1. Scope boundary — FCT only after named AOI / X-ray / electrical / FAI lines; FCT is not a rewrite of those gates.
  2. Volume class — bench checklist / reusable nest / custom automated fixture (pick one primary).
  3. Procedure rev — attach file; list steps and limits; name exclusions.
  4. Firmware rev — image identity, flash owner, verify method.
  5. Fixture ownership — buyer-owned, EMS-owned, or shared; who pays pogos/spares; lead time for fixture build.
  6. Cycle time class — target minutes per board class (order-of-magnitude for quoting, not a fabricated plant guarantee); overtime / second-shift rules if relevant.
  7. Utilities — power rails available at the station, compressed air, RF shielding needs, barcode.
  8. Data package — log format, fail codes, retention, privacy for serials.
  9. Sibling gates — confirm FQC/packing and flying-probe/ICT remain separate quote lines with their own coverage text.
  10. Respin rule — what happens to fixture and script NRE when layout or connector moves.

Refuse lone phrases like “100% functional test” or “power-on included.” Force method class, procedure rev, firmware identity, and fixture ownership onto the quote so overseas buyers can compare China EMS lines without guessing.

Practical takeaway

Power the board for FCT when you need end-use behavior proof — after the visual and structural-electrical gates you already named. Scale from bench to reusable nest to custom fixture as layout freezes and volume rises. Use FCT to catch firmware, protocol, out-of-band wrong values, intermittent mates, and sequencing issues that opens/shorts tests will not see. Do not let FCT replace AOI, X-ray, bare-board ET, FQC packing, or FAI setup release. Design power/sense points, debug headers, fixture datums, and golden-board rules — confirm mechanics with the plant. Lock pass/fail limits, firmware rev, fixture ownership, cycle-time class, and data logs in the RFQ. That is how XFPCB-style overseas sourcing keeps functional-test quotes honest, bounded, and comparable without inventing prices or yield theater.

Functional circuit testing FAQ

When should I power the board on for FCT?

After the structural and cosmetic gates named for that revision — typically AOI (and X-ray where BTCs need it), a named electrical method if used (flying probe, ICT, or equivalent), and any first-piece setup release the PO requires. Then run a revision-locked powered procedure with numeric pass/fail limits. Do not use FCT as a substitute for bare-board netlist test or SMT cosmetic AOI.

Bench, reusable nest, or custom fixture — which FCT class?

Bench for prototypes and early NPI while layout and firmware still move. Reusable nest plus script when outline and test-point map are mostly frozen but volume is still low. Custom automated fixture when cycle time and lot size make hand probing the bottleneck and the layout is under change control. Name the class in the RFQ so bidders price the same work.

What does FCT catch that flying probe or ICT miss?

Firmware boot and image identity, protocol bring-up, wrong values that still net within a crude structural band, intermittent connector seating, and rail sequencing or protection trips under load. Structural electrical tests prove connectivity and many passives; FCT proves powered behavior under a defined stimulus.

What should DFT for FCT include?

Dedicated power/return and sense lands, programming/debug headers with pinout on the assembly drawing, fixture fiducials/tooling holes and clamp keep-outs, a connector mate strategy, and golden-board criteria with a re-verify interval. Confirm mechanics with the EMS that builds the fixture — do not treat guidance as a universal plant capability claim.

What belongs in an FCT RFQ for comparable China quotes?

Procedure rev with numeric limits, firmware image identity and flash owner, fixture ownership and spare/pogo responsibility, cycle-time class, data-log format and retention, explicit boundaries vs AOI/X-ray/flying-probe/FQC/FAI, and a respin rule when layout or connectors move. Reject lone phrases like “100% functional test” or “power-on included.”

Is this the same as flying-probe, FQC, FAI, or turnkey posts?

No. This blog is the powered FCT when-to-power-on, DFT, and RFQ playbook. Flying probe covers fixtureless electrical method selection; FQC covers final appearance and outbound packing; FAI is first-piece production-setup release; turnkey vs consignment is kit ownership. Keep those boundaries — do not merge them into one RFQ note.