IPC Multilayer PCB Classification Guide — Type, HDI, Class for RFQs

RFQ packages that only say “multilayer PCB, Class 2” leave China CAM guessing which construction you meant. IPC does not sell a single “multilayer grade” stamp. It frames design language across generic rules, rigid organic board types, and high-density interconnect (HDI) structures — then separately frames fabrication and assembly acceptance classes. Buyers and engineers who mix those vocabularies get mismatched quotes: a Type 3 through-hole stack priced as if it were sequential HDI, or a Class 3 inspection ask sitting on a Class 2 process window. This guide paraphrases factory-practical meaning for RFQs — not a legal reprint of IPC tables — so you can lock stack type, via architecture, layer-count intent, and class expectations before bidders invent them. Soft CTA only. Live XFPCB Class 2 vs Class 3 and IPC Class 3 fabrication pages already own deep class / inspection comparison — name those lanes in prose; do not clone them. Industrial manufacturing and wiring-density siblings stay prose pointers too. No competitor brands. No invented XFPCB certificates, turnaround days, dollar menus, or capability dashboards.

Why classification language shows up on China fab quotes

Export RFQs often collapse three different ideas into one adjective:

1. Construction type — how layers connect (through vias only vs blind/buried vs microvia build-ups).
2. Density / process family — conventional rigid multilayer vs HDI sequential lamination.
3. Acceptance class — how tightly fab and assembly inspect and accept the finished product.

Those ideas live in different IPC document families. Treating “IPC multilayer Class 3 HDI” as one checkbox is how travelers get rewritten mid-lot. CAM needs a stack note that names via architecture and layer count, plus an acceptance line that names document + class for fab (and assembly when PCBA is in scope). Spec sheets and marketing PDFs that only say “IPC compliant multilayer” do not freeze either field.

Factory translation: classification is a shared sketch language for stack and process intent. It is not a certificate hanging in the lobby, and it is not a substitute for Gerbers, stackup PDF, drill map, and fab notes.

IPC-2221 — umbrella design rules, not a board type

IPC-2221 is the generic printed-board design framework. In buyer speech it covers spacing, annular ring intent, dielectric clearance thinking, and the electrical/mechanical considerations that every rigid design inherits. It does not by itself classify your board as “Type 3” or “HDI Type II.”

On an RFQ, 2221-class language shows up as design-rule floors and notes (“follow IPC-2221 for general conductor spacing unless drawing overrides”). Do not paste chapter tables into the PO. Freeze overrides that matter for your product — creepage for industrial contamination, controlled impedance nets, minimum annular ring if you tighten beyond fab default — and let the sectional standards below name the construction.

If your package only cites 2221 with no type and no class, bidders still guess construction and acceptance. Use 2221 as the foundation line when you need it; finish the traveler with type and class.

IPC-2222 — Type 3 and Type 4 rigid multilayer (factory meaning)

IPC-2222 is the sectional design language for traditional rigid organic boards with general-purpose feature sizes. The type labels buyers hear most often on multilayer jobs:

Type 3 — multilayer without blind or buried vias. All interconnects are plated through-holes spanning the finished board. This is the workhorse stack for industrial controls, many communication boards, and cost-sensitive multilayer products. Yield and process maturity are high when aspect ratios and copper balance stay inside normal fab windows. A Multilayer PCB Guide traveler that stays Type 3 is usually the cheapest path that still gives solid reference planes.

Type 4 — multilayer with blind and/or buried vias. Blind vias connect outer layers to selected inner layers; buried vias connect inner layers without reaching the outer surfaces. These structures raise routing density and shorten some paths under fine-pitch BGAs or dense connectors, but they add registration, lamination, and drill complexity. Quotes jump when the drawing shows Type 4 without saying which layers the blind/buried nets touch.

Buyer traps:

• Writing “multilayer with buried vias preferred” without a via map forces CAM to invent a Type 4 stack — or to ignore the note and price Type 3.
• Calling a board “HDI” when it only has a few mechanical blind vias. HDI usually implies microvia / sequential build-up language under IPC-2226, not every blind hole.
• Asking for Type 4 density while holding Type 3 lead time and Class 2 price expectations.

Factory-practical lock: state Type 3 or Type 4, attach a stackup that shows via spans, and name finished copper and aspect-ratio intent. Confirm-with-fab on drill and plate windows; do not invent µm plating menus as plant claims.

Layer count vs classification — related, not identical

Layer count is a quantity. Classification is a construction and process story. An 8-layer Type 3 board and an 8-layer HDI Type III board share a layer number and almost nothing else in CAM risk.

Practical mapping buyers use:

• 4–8 layers, through vias only — usually Type 3 language unless the drawing forces blind/buried.
• Higher layer counts with through vias — still Type 3 in 2222 speech, but registration, copper balance, and press cycles tighten. When the stack grows into High Layer Count PCB territory, freeze balance, press count intent, and test coupons even if the type label stays Type 3.
• Blind/buried on a conventional core — Type 4; say which layers.
• Microvia build-ups / sequential lamination — move the conversation to IPC-2226 HDI types, even if total layers look “only” 8 or 10.

Do not use layer count as a substitute for type. “12-layer Class 3” still leaves CAM free to assume all-through or to invent build-ups. Pair layer count with via architecture every time.

IPC-2226 — HDI types in RFQ English (paraphrase, not a table dump)

IPC-2226 standardizes design language for high-density interconnect boards that rely on microvias, blind/buried structures, and often sequential lamination. Buyer shorthand (factory paraphrase — verify against your drawing and the current IPC text your program cites):

• Type I — single build-up microvia layer(s) to a core; simplest HDI form. Through vias may still appear. Used when one microvia layer unlocks BGA escape without a full sequential maze.
• Type II — microvia build-up over a core that itself includes buried vias. Hybrid density: buried nets inside the core plus laser microvias on the outsides.
• Type III — multiple sequential build-up layers (more than one microvia layer on a side in common speech). Highest process complexity: repeated laser drill and lamination cycles, tighter registration, more coupon and reliability scrutiny.

Exact “1[C]0 / 1[C]1 / ≥2[C]…” notation belongs on the stackup note when your design team uses it. This article will not reprint copyrighted IPC type tables. What RFQs need is clear: HDI type intent, microvia layer count per side, whether the core has buried vias, and whether any through vias remain.

When density is the driver, an HDI PCB process note beats vague “fine pitch capable” adjectives. Wiring-density tactics (fan-out, via-in-pad policy, escape routing) live on their own XFPCB density sibling as a prose pointer — this page only locks how you name the HDI construction so quotes stay comparable.

Class 2 vs Class 3 at high level (product lock, not type lock)

Acceptance class is orthogonal to Type 3 / Type 4 / HDI type. Class answers “how tight is workmanship and inspection,” not “how many microvia layers.”

At buyer level:

• Class 2 — general electronic products where continued performance is expected and field replaceability is often acceptable. Many China fab defaults lean here when the RFQ is silent.
• Class 3 — high-reliability / harsh-duty expectations: tighter workmanship criteria and deeper inspection when downtime or safety cost justifies it.

Cite document families correctly. Bare-board fab commonly references IPC-6012 (with IPC-A-600 visual as needed) plus an explicit class. Assembly references IPC-A-610 with its own class. Writing only “IPC Class 3” without a document number invites receiving fights.

Deep Class 2 vs Class 3 comparison and Class 3 fabrication nuance already live on XFPCB class and Class 3 fabrication pages — prose pointers only. Here the rule is short: put type on the stack line; put class on the acceptance line; do not let one substitute for the other. Industrial manufacturing guidance that maps plant environment → class also stays on its published industrial sibling as a prose pointer.

Over-classing a mild Type 3 consumer-adjacent board buys scrap and calendar. Under-classing a Type III HDI server or industrial control board understates microsection and coupon expectations. Match class to failure cost; match type to routing architecture.

What to freeze on China fab RFQs

Comparable quotes need the same traveler. Soft phrases (“HDI preferred,” “multilayer IPC,” “Class 3 if possible”) produce non-comparable bids. Lock fields in writing, then attach Gerbers and notes through Manufacturing Files so every bidder prices the same package.

RFQ lock list (classification-focused):

1. Document + construction type — IPC-2222 Type 3 or Type 4, or IPC-2226 HDI Type I / II / III intent (plus microvia layer count / buried-core yes-no when HDI).
2. Layer count and stackup PDF — finished copper outer/inner, dielectric intent, impedance nets and coupon yes/no.
3. Via map — through only; blind/buried spans; microvia diameters and capture pads at drawing intent (confirm-with-fab process windows — no invented plant menus).
4. Acceptance — IPC-6012 Class X for fab; IPC-A-610 Class X when assembling; revisions preferred.
5. Test / inspection package — electrical method; AOI; microsection / coupon expectations tied to class and HDI risk; no silent downgrade without EQ.
6. Process family notes — sequential lamination count intent for HDI; via-fill / cap where required; aspect-ratio floors that match copper and class.
7. No invented XFPCB capability tables — laser, registration, and plating claims come from bidder confirmation against your frozen notes.

PCB Manufacturing still follows DFM → inner → press → drill/plate → outer → mask/finish → electrical → FQC. Classification only tells CAM which gates must stay open. Technical capability pages can help you ask better confirm-with-fab questions; they do not replace typed locks on the PO.

Common RFQ failure modes (and how to stop them)

• Type label missing, density adjective present. “Fine pitch multilayer” gets priced as Type 3 until late EQs discover buried vias. Fix: type + via map before quote scorecards.
• HDI type vs Type 4 confusion. Mechanical blind vias ≠ sequential microvia HDI. Fix: name 2222 Type 4 or 2226 HDI type explicitly.
• Class without document. Receiving argues A-600 vs 6012 vs A-610 language. Fix: document + class on fab and assembly lines separately.
• Layer count used as HDI proof. High layer Type 3 is not Type III HDI. Fix: separate fields.
• Silent default to Class 2 process windows under a Class 3 heading. Fix: inspection package and coupon callouts on the same page as class.
• Competing bidders with different assumed build-ups. Fix: one frozen stackup shared to all; EQ required before any type or class change.

Soft close — freeze type and class, then ask for a quote

When the stack type, via architecture, layer count, and acceptance class are frozen on one traveler, China fab quotes become comparable instead of creative. Attach the manufacturing file pack, keep Class 2 vs Class 3 depth on the dedicated class pages, and keep industrial environment and density tactics on their own published guides. When you are ready to send that frozen package, use How to Place an Order and ask bidders to confirm type, class, and via spans against your notes — not against brochure adjectives. Soft CTA only; confirm-with-fab on every plant-specific number this article refused to invent.