Overseas buyers awarding China fab and PCBA often inherit a soft traveler line — “testing included” — then discover after dock that visual gates substituted for electrical proof, bare-board e-test was sampled, or functional coverage meant power-on only. Industry posts that list ICT fixtures and manufacturing-defect analysis, then warn that bad batches destroy brands, still leave export procurement without a why-and-what-to-lock frame: the cost of escaped defects across an ocean, the difference between inspection and electrical / functional proof, RFQ language that freezes gates before award, how to read China quote test line items, and how Class 2 vs Class 3 should change test intensity. This page owns that buyer frame only. Sibling XFPCB lanes already own the methods decision matrix, the six QA-check when-to-buy list, AOI depth, and single-defect lanes such as solder bridges — name those lanes in prose; do not clone them. No competitor brands. No invented XFPCB yield or escape-rate percentages, lab awards, or fake fixture menus.
Why escaped defects cost more after a China award
A defect that leaves the China plant does not stay a plant scrap ticket. It becomes freight, customs delay, line-down time at your contract manufacturer or OEM, field returns, and — on medical, industrial, or aerospace-adjacent programs — customer trust damage that no credit memo repairs. The economic asymmetry is the point of this post: the cost to catch a net open, a missing BGA ball, or a wrong firmware image before ship is almost always smaller than the cost of the same escape after ocean transit.
Buyers sometimes treat testing as a line-item to compress so the fab / PCBA quote wins on unit price. That compression is rational only when you know which escapes you are accepting. Soft “testing included” language usually means house defaults — sample optical gates, first-article X-ray, flying probe assumed on bare board only, functional as “power on and see.” Those defaults are not malice; they are how factories fill blank travelers. The buyer who awards without freezing gates is the one who owns the escaped-defect bill.
For export programs, distance amplifies the asymmetry. Rework loops that take a day with a local fab become weeks with a China lot already on the water. Prototype and early pilot lots — where Prototype PCB Assembly volume is still low — are especially vulnerable: fixture NRE looks expensive relative to unit count, so electrical coverage gets deferred, then the same soft traveler rides into volume. Write the escape economics into the award decision, not into a post-dock CAPA.
Inspection is not electrical proof — and neither is “power on”
Three buyer jobs get collapsed into one word on weak RFQs. Keep them separate so China quotes stay comparable.
Inspection answers “does the board look and measure like the intended construction and placement?” Optical gates (AOI), solder-paste inspection (SPI), and X-ray for hidden joints catch placement, bridging, voids, and many assembly process escapes. They do not prove every net continuity or isolation. Deep AOI traveler essays live on the dedicated AOI sibling; single-defect lanes such as solder bridges live on their own pages — prose pointers only. When hidden joints need non-optical evidence, open X-ray inspection as the capability lane, not as a synonym for “tested.”
Electrical testing answers “do the nets connect and isolate as designed?” Bare-board electrical test (often called e-test) on the fab panel, flying probe on bare or assembled boards, and in-circuit test (ICT) with a bed-of-nails fixture are electrical jobs. They catch opens, shorts, and many wrong-value / wrong-orientation faults that cameras miss. They do not prove that the product boots and meets functional limits under load.
Functional circuit test (FCT) answers “does this assembly behave as the product must in its intended use?” Power rails, firmware load, sensor stimulus, communication links, and pass/fail limits you own. “Power on and see” is not FCT. Soft FCT language is how bring-up failures leave the plant looking green on the traveler.
Capability menus and process windows for these gates live under PCB board testing and inspection and Technical Capabilities. This page does not rewrite the methods encyclopedia or the six-check QA matrix — those siblings already own how-to and when-to-buy depth. Here the rule is simpler: never let an inspection noun stand in for electrical proof, and never let electrical continuity stand in for product function.
What to lock on the RFQ before you award China fab / PCBA
Export quotes diverge when test language stays soft. Paste comparable locks so every bidder answers the same traveler. Attach drawings, netlists, and any fixture / FCT ownership notes with Manufacturing Files before “testing TBD” quotes are treated as comparable.
- Bare-board electrical test — 100% netlist e-test on fab panels unless your PE explicitly accepts a documented sample plan. “Visual OK” is not e-test. Ask what happens on opens / shorts: scrap, repair, or quarantine — and who signs disposition.
- AOI / SPI gates — which stages (post-paste, post-placement, post-reflow), sample vs 100%, and whether AOI fail disposition is repair-and-reinspect or hold. Do not paste the AOI sibling essay; freeze the gate on the traveler.
- X-ray gates — which packages or joints (BGA, QFN, etc.), first-article vs lot coverage, and what void / bridge criteria your controlled document already uses. Soft “X-ray available” is not a gate.
- Flying probe vs ICT by volume — early SMT PCB Assembly and prototype lots often earn Flying probe coverage without bed-of-nails NRE; volume lots may earn ICT fixture payback when net count, repeat rate, and takt justify it. Write volume thresholds and who owns fixture NRE / lead time — do not invent XFPCB fixture price menus.
- FCT scope — rails, interfaces, firmware revision, stimulus, and numeric pass/fail limits you own. Name who writes and maintains the FCT procedure. “Functional test included” without scope is not comparable.
- Sample vs 100% — for every gate, state coverage. Sample AOI + sample FCT is a different award than 100% e-test + 100% AOI + lot FCT. Silent sample defaults are how escapes leave looking “tested.”
- Class and acceptance references — IPC Class 2 vs Class 3 (and any drawing callouts to IPC-A-600 / IPC-6012 / IPC-A-610) change how aggressively defects are judged; see the intensity section below. Class is not a plant badge and not a substitute for naming the gates.
- Turnkey ownership — when the award is Turnkey PCB Assembly, say who owns bare-board e-test evidence, who owns ICT / flying-probe fixtures, and who owns FCT fixtures and golden units. Split fab + assembly awards without shared test ownership are a classic escape path.
Do not invent XFPCB escape-rate dashboards, lab awards, or dollar / TAT menus as plant law. Generic gate + coverage + ownership locks are enough for comparable RFQs.
How to read a China quote’s test line items
A competitive unit price with a vague “QC / testing” lump is not a comparable quote. Train the sourcing eye on a few tells.
Lumped “testing included.” Ask for a breakdown: bare-board e-test, AOI stages, X-ray scope, flying probe or ICT, FCT. If the bidder cannot map the lump to gates, the traveler will inherit house defaults after PO.
Fixture NRE missing on ICT quotes. ICT without fixture cost / lead time either assumes you already own the fixture, assumes flying probe instead, or will reopen NRE after award. Clarify before you score the bid.
“AOI” with no stage or coverage. Post-reflow sample AOI is not the same commercial promise as 100% AOI at paste + placement + reflow. Coverage belongs on the line item or the traveler attachment.
“X-ray available” vs “X-ray on every BGA.” Availability is marketing language. Lot coverage and package list are award language.
Functional = power-on. If the quote does not mention your rails, interfaces, or firmware, assume bring-up risk stays with you unless you freeze FCT scope.
Sample plans buried in footnotes. A low unit price often hides sample e-test or sample FCT. Pull sample percentages into the comparison sheet next to the unit price — that is the escaped-defect trade you are buying.
No fail disposition. Quotes that never say scrap / repair / quarantine leave disposition to tribal knowledge on the floor. Ask for the disposition path on electrical and FCT fails.
Score China bids on gate + coverage + ownership + disposition, not on whether the word “test” appears. Soft next step after the traveler is clear: send the RFQ through How to Place an Order with Manufacturing Files attached — after test locks freeze, not after a lump-sum QC line reopens sample defaults post-award.
Class 2 vs Class 3 — how test intensity should change
IPC Class 2 (dedicated service electronic products) and Class 3 (high-performance / harsh-environment electronic products) are acceptance and workmanship levels you write on drawings and POs. They are not plant wall certificates and not the same thing as AS9100 or ISO registration. The live Class 2 vs Class 3 buyer guide owns workmanship depth — prose pointer only. Here the testing-intensity rule is what matters for overseas awards.
Class 2 intensity (typical export industrial / commercial). Bare-board 100% e-test remains the default expectation for many fab awards. AOI coverage is still worth freezing — Class 2 does not mean “visual only.” Flying probe or ICT follows volume economics. FCT scope tracks product risk: a simple power board may need less than a networked controller. Sampling may be acceptable on some gates when your PE documents the plan — but sampling must be written, not assumed.
Class 3 intensity (when product risk warrants it). Expect tighter workmanship criteria and, in practice, less tolerance for soft sample defaults on critical gates. Buyers often move toward 100% coverage on electrical and optical gates that Class 2 programs might sample, add more X-ray on hidden joints, and demand named FCT limits with stricter fail disposition. Microsection / coupon evidence and process capability questions rise. Do not invent XFPCB Class 3 surcharge percentages; write the intensity as coverage + evidence + disposition, then let bidders price the traveler.
AS9100 / aerospace-adjacent programs. Quality-system registration supports process control; it does not replace named test gates on the RFQ. When aerospace or high-reliability siblings apply, keep system language on those pages and keep gate locks on this traveler.
Class without gates still escapes. Gates without Class still argue at MRB. Write both.
Soft next step
Treat PCB testing as the overseas buyer’s escaped-defect insurance — not as a methods brochure and not as a free house default. Separate inspection from electrical proof from functional proof, freeze bare-board e-test / AOI·SPI·X-ray / flying-probe-vs-ICT / FCT / sample-vs-100% language before you score China quotes, read lump-sum QC lines as incomplete, and match Class 2 vs Class 3 intensity to product risk. Soft next step when the traveler and Manufacturing Files are clear: route the award through How to Place an Order with test ownership written — after the gates freeze, not after an ocean transit teaches you what “testing included” omitted.