Channel-loss budgets already list dielectric, copper geometry and vias. At GHz, the copper surface joins that list: roughness that was invisible at tens of megahertz starts to move conductor loss when skin depth sits in the same order as the tooth profile. The useful factory question is not a lecture on skin effect—it is what to write on the stack note beside Dk/Df so the fab does not pull standard foil by habit.
This post is that callout gate for overseas buyers and engineers. HTE versus low-profile reliability tradeoffs, ED drum-side treatments, and the full channel-loss lever map are sibling posts. Here we only decide when roughness must be named for GHz nets.
Skin effect makes the surface the conductor
As frequency rises, current crowds toward the copper surface. When the skin depth approaches the roughness height of the foil tooth, the current path lengthens and conductor loss rises. Below roughly the low-GHz region the difference between common foil grades is often small on short nets; as frequency and path length grow, the gap opens. That qualitative curve is why RF and SerDes stack notes started listing foil profile at all.
Do not paste a single “above 1 GHz always upgrade foil” rule without path length, layer, and loss budget. Short, well-referenced nets on FR-4-class builds may still be foil-agnostic; long backplane channels and microwave lines usually are not.
Roughness is also a process, not only a foil SKU
Inner-layer oxide or oxide-replacement (often still called brown oxide in shops) roughens copper for adhesion before press. That process tooth is part of the loss story. Buying “smooth foil” and then accepting an aggressive oxide recipe can return roughness you thought you paid to avoid. The stack note should carry foil grade and any adhesion-treatment constraint the SI owner cares about—or accept that peel strength and loss will be traded in EQ.
What to write on the stack note
For nets in the loss budget:
- Laminate family with Dk/Df at a stated frequency and method.
- Copper weight and foil profile family the laminate is built with (standard / RTF / VLP / HVLP—or the supplier’s equivalent language).
- Which layers carry the critical GHz paths (outer microstrip sees foil + mask; inner stripline sees foil + resin).
- Whether oxide treatment is constrained or left to the fab’s qualified process.
Our High Frequency PCB and Impedance Control PCB pages are the construction and measurement seats. Foil grade without impedance and laminate callouts is an incomplete RFQ.
Outer versus inner layers
Microstrip on the outer layer sees treated foil on one side and solder mask on the dielectric face of the trace. Stripline sees foil teeth into resin on both sides of the strip in many constructions. Saying “use VLP everywhere” without saying which layers carry the GHz nets wastes money on power planes that never needed it. Call the critical layers by name.
When standard foil is still enough
- Digital edges whose harmonics and length do not spend the loss budget.
- Short interconnects inside a module where connector and via dominate.
- Cost-sensitive builds where you will fix loss with length, reference, or laminate before foil premium.
Upgrade foil when calculation or measurement shows conductor loss is the remaining lever after dielectric and geometry are set—not because a blog listed VLP as “modern.”
What we are not claiming
No invented dB/inch tables, no Df numbers from a competitor’s brown-oxide demo as universal truth, no claim that smoother foil always wins peel and etch, and no replacement for the HTE/low-roughness reliability post. Put foil roughness on the GHz stack note beside Dk/Df when the channel needs it. Leave it off when the budget does not.