Hardware startups lose weeks on “fast-turn” PCB prototypes when the package maturity does not match the stage. EVT needs debug room and complete-but-flexible files; DVT needs near-final stackup, BOM, and test depth; a pilot run needs locked revision, panel notes, programming, labeling, and pass/fail criteria a factory can repeat. Speed only helps when Gerber, BOM, CPL, assembly drawing, and test intent describe the same revision — and when the RFQ states what is frozen versus what is still allowed to change.
This note is for overseas NPI engineers and buyers preparing EVT → DVT → pilot builds at a China fab: a file/BOM/test maturity table, the RFQ traps that stall CAM (revision lock, alternates, panel notes, programming/labeling), and a practical package checklist. It is not a generic quick-turn service pitch, and it is not a substitute for your product-validation plan.
What “ready for fab” means at each stage
Treat each build as a different question, not the same “prototype” SKU with a different quantity.
| Stage | Question the build must answer | PCB / PCBA posture | File / BOM posture | Test posture |
|---|---|---|---|---|
| EVT | Does the core design work? Where do we debug? | Debug access, test points, programming headers; layout may still move | Complete zip, same revision across Gerber/BOM/CPL; stackup and MPNs can still flex with documented deltas | Power rails, bring-up, sensors, comms — expect learning, not yield theater |
| DVT | Does the production-intent design meet product requirements? | Near-final placement, connectors, stackup, enclosure constraints | Near-final BOM with approved alternates; stackup and impedance notes confirmed | Reliability, thermal, RF/EMI as needed, mechanical fit — fewer “maybe” parts |
| Pilot / PVT | Can the factory build, inspect, program, label, and pack this repeatedly? | Locked design; panelization and process notes intentional | Revision-locked Gerber + BOM + CPL + drawings; no silent feeder swaps | Fixture / script / pass-fail, labeling, traceability, packaging — process proof |
A common failure mode is shipping an EVT-level zip with a pilot-level schedule: CAM asks for panel notes and firmware hashes that do not exist, or assembly builds “whatever is newest in the shared drive.” Name the stage on the RFQ so both sides know what maturity you claim.
💡 Factory gain: Put
Stage: EVT | DVT | PilotandRevision freeze: Gerber/BOM/CPL/firmware = REV-Xin the RFQ cover note. Ambiguous “prototype ASAP” is how mixed revisions get built.
Package maturity table — files, BOM, test
Use this as a release gate before you hit send. “Required” means the fab or CM cannot start without inventing defaults you will later reject.
| Package item | EVT | DVT | Pilot |
|---|---|---|---|
| Gerber / ODB++ + drill map | Required, flexible | Production-intent | Locked |
| Layer / stackup / finish / IPC class notes | Preliminary OK if stated | Confirmed | Locked on traveler |
| BOM with MPN + package + DNP | Required | Near final + approved alternates | Locked AVL |
| CPL / pick-and-place + polarity | Required | Verified vs drawing | Locked |
| Assembly drawing / polarity map | Strongly recommended | Required | Required |
| Panelization / array notes | Optional | Recommended | Required |
| Test plan (power, program, pass/fail) | Basic bring-up | Detailed | Final criteria |
| Programming file / hash / version | Recommended if MCU | Required if programmed at CM | Final released image |
| Labeling / SN / packing | Optional | Recommended | Required |
| First-article / FAI expectation | Often informal | Agree sample size | Formal hold before remaining qty |
EVT packages fail most often on inconsistent revisions and vague BOM lines (“10k 0402”, “USB-C connector”) with no MPN. Pilot packages fail most often on missing process artifacts: panel drawing, programming station notes, label artwork, and who owns functional test.
China-fab RFQ traps that burn startup schedules
These are not marketing checklists — they are the clarification emails that eat your “5-day” lead time before lamination starts.
1. Revision lock (or the lack of one)
If Gerber REV-B, BOM REV-C, and CPL from last Tuesday share one zip name, CAM will stop or guess. Pick one assembly revision, stamp every file, and write “build only REV-X” on the PO. After any layout change, re-zip the whole set — do not “just replace the Gerbers.”
2. Alternates without an AVL rule
Fast builds die on a single unavailable MPN. For DVT and pilot, list approved alternates (or “no substitutes”) per critical line: MCU, connectors, magnetics, RF modules, power FETs. Silent shop substitution on pin-compatible footprints is how EVT “worked” boards become DVT bricks.
3. Panel notes left blank
Bare-board prototype panels can be shop-standard. Pilot and many DVT PCBA runs need edge rails, fiducials, tooling holes, breakaway style, and depaneling method. If you care about board outline yield or fixture alignment, put panel constraints in the fab notes — do not discover them after stencil cut.
4. Programming and labeling treated as “after” work
If the CM must flash firmware, you need binary (or approved link), version string, checksum/hash, connector/pads used, and fail disposition. If units need SN labels or regulatory marks, artwork and placement belong in the package before pilot. Leaving these as Slack messages creates two builds: the electrical one and the one you can ship to beta customers.
5. Stackup and impedance as hallway talk
Controlled-impedance or high-speed interfaces need stackup and target impedance in writing for DVT onward. Verbal “standard 4-layer FR-4” is fine for many EVT boards; it is not fine when USB, DDR, or RF later blame “the fab.”
EVT build habits that save the next two spins
Keep investigation hardware on the board until DVT proves you do not need it:
- Enough test points on rails and key buses
- Programming / debug access that does not require rework under a shield
- Clear silk for pin-1 and connector keying
- DNP options for bring-up straps and current-sense shunts
Removing every debug aid to “look production” on the first EVT spin is how teams burn a second fab cycle on a problem a header would have shown in an hour.
Also separate bare PCB vs PCBA intent. Mechanical fit and early copper checks can be bare board; firmware, power, and sensor work almost always need assembled units with a real BOM — not a hand-stuffed one-off treated as process evidence later.
DVT: freeze what product validation depends on
By DVT, enclosure mounts, connector locations, antenna keepouts, thermal parts, and critical MPNs should stop thrashing. Update the maturity table honestly: if the BOM still has three candidate PMICs, say so and limit which lines are frozen. Ask the fab/CM for DFM/DFA on the production-intent stack — spacing, annular ring, solder-mask bridges, BTC inspection access — so pilot is not the first time process risk appears.
Agree how substitutes are approved (email deviation vs formal ECO). A “use anything in stock” note belongs on EVT scavenger hunts, not on DVT reliability lots.
Pilot run: process proof, not another design weekend
Pilot (often tied to PVT) validates repeatability: paste/print windows, placement yield, inspection coverage, programming yield, labels, packing, and traceability. The design should already be the one you intend to buy again.
Practical pilot package extras:
- Locked Gerber + BOM + CPL + assembly drawing under one rev ID
- Panel drawing or written panel constraints
- Programming work instruction + firmware identity
- Label placement drawing + SN format
- Pass/fail functional script and who signs ship-to-stock
- Clear rule: ECO stops the line until a new locked package is released
Do not use pilot quantity to try a new MCU footprint “while we are at it.” That is a new EVT wearing a pilot PO number.
RFQ cover note — copy/adapt
A short cover note outperforms a 40-page slide deck nobody opens:
- Stage: EVT / DVT / Pilot
- PCB P/N + assembly P/N + single revision for this build
- Layer count, thickness target, finish, soldermask/silkscreen colors (as required)
- Bare board only vs PCBA; consigned vs turnkey BOM
- Alternates policy: AVL attached / no substitutes / contact buyer
- Panel: shop default OK vs attached constraints
- Programming / labeling / packing: yes-no + files attached
- Test: customer-owned vs CM script + first-article hold yes-no
XFPCB and similar China fabs move fastest when the zip answers those lines without a discovery call. Incomplete packages do not get faster because the calendar says “startup.”
Closing — match maturity to the stage
Fast-turn PCB prototypes shorten hardware loops only when EVT leaves room to learn, DVT freezes product intent, and pilot locks the process artifacts. Use the maturity table before every RFQ; call out revision lock, alternates, panel notes, and programming/labeling explicitly. That is the difference between a five-day fab queue and a five-day email thread about which files were “current.”