PCB prototype process is not one build with a pretty photo. It is a staged maturity path — proof of concept, visual or Gerber build, working board, then near-production functional — that catches cost before pilot and mass lots lock the wrong stack, finish, or acceptance depth. Soft brochure pages list “benefits” as save time, save money, improve design. China fab and PCBA buyers need sharper language: what each stage must prove, which lab and test gates belong on the RFQ at that maturity, and what skipping a stage actually costs when EQ storms, kit shortages, and Class arguments hit the traveler. Partner-selection checklists live elsewhere. Quick-turn speed economics live elsewhere. Fabrication design-to-delivery maps live on their own pages. This guide is stage maturity and cost catch for prototype lots — without competitor brands, CAD plugs as ads, or invented XFPCB dollar and TAT menus.
Why stages beat a single “prototype” line on the RFQ
Calling every five-piece lot a “prototype” hides maturity. A PoC that only proves the power rail is viable is not the same buying problem as a near-production functional board that must match pilot laminate, finish, and A-610 criteria. When maturity is unnamed, fabs quote the cheapest path that still ships copper; assembly houses assume kit completeness you do not have; and buyers compare unit prices across unlike proofs.
Write the stage on the RFQ. Then write what that stage is allowed to prove — and what it is not allowed to skip. Stages can overlap on complex programs (a visual Gerber build may ride beside a working breadboard), but each award still needs a named proof goal. Otherwise the lot becomes calendar theater: boards arrive, nothing was proven, and the next respin funds the lesson you already paid for.
Stage 1 — Proof of concept: prove the function is viable
A PoC prototype focuses on the primary function without every enclosure, cosmetic, or production process finish. For a China fab buyer, the PoC should prove:
- The circuit topology can meet the core electrical intent (power, critical signal path, or sensor loop) under a stated load.
- Major topology risks are visible early — not after a full multilayer Gerber freeze.
- Scope is deliberately incomplete: temporary fixtures, bench wiring, or non-final connectors are acceptable if named.
What a PoC should not pretend to prove: producibility of the final stack, Class 3 microsection readiness, cosmetic brand match, or full AVL kit readiness. Awarding a PoC as if it were pilot acceptance is how teams skip straight into near-production language with PoC maturity.
RFQ gates that belong here. Continuity / smoke-level electrical checks; basic functional pass/fail against a short script; thermal spot checks only if heat is the PoC risk; explicit note that finish, Tg, and impedance may be temporary. Keep Manufacturing Files light but honest — even a PoC Gerber set should state temporary finish and “not for pilot acceptance.”
Cost of skipping. Teams that jump from napkin to “working” multilayers often discover the function was never viable — after paying for layer count, controlled impedance, and partial kits they did not need yet.
Stage 2 — Visual / Gerber build: prove form, stack, and affordability
The visual or Gerber build is the earliest fab-shaped artifact: CAD release to Gerber or ODB++, then a board that shows outline, stack intent, pad geometry, and whether the construction is affordable enough to continue. CAD tool choice is a team preference, not a brand pitch — ship clean layers and fab notes either way.
For a China fab buyer, this stage should prove:
- Mechanical fit: outline, keep-outs, connector locations, and thickness against the enclosure or next assembly.
- Construction realism: layer count, via plan, and whether HDI PCB or flexible PCB paths are actually required — or whether a simpler rigid stack still meets the proof goal.
- Quote realism: stock vs buy laminate, named surface finish, copper weight — so “affordable” is not a soft FR-4 label.
RFQ gates that belong here. Complete Gerber/ODB++ with fab notes; electrical test depth appropriate to bare board (often flying-probe continuity/isolation on prototype quantities); stack and finish locked for this stage even if pilot may change later; Class language if you will reject boards against IPC-6012 / A-600 criteria. Do not demand full assembly AOI/X-ray depth on a bare visual lot.
Cost of skipping. Jumping past a Gerber build into fully populated working boards hides fab-side geometry and stack mistakes inside assembly scrap. The assembly house cannot solder a pad geometry that never should have left CAM.
Stage 3 — Working prototype: prove the board does the job
A working prototype is a functional board with the intended features populated — usually via prototype PCB assembly or a mixed consign / turnkey kit. The proof goal shifts from “copper looks right” to “the product behavior exists under lab conditions.”
For a China fab buyer (and PCBA buyer), this stage should prove:
- End-to-end functions against a written script — not a demo that only works on one golden unit.
- Design errors that only appear when parts are placed: polarity, footprint, decoupling, power-up sequencing, firmware bring-up hooks.
- Which process risks are design vs process: SMT PCB assembly yield, through-hole mix, or hidden-joint inspection needs.
RFQ gates that belong here. Named assembly class (IPC-A-610) separate from fab class; AOI default; X-ray depth for BGA/QFN when those packages exist — see PCB board testing and inspection and X-ray inspection for depth language buyers should paste into scopes; functional test ownership (who writes the script, who fixtures, who owns fail disposition); kit ownership and AVL substitution rules. Flying probe on the bare board remains useful before populate when netlist risk is high.
Significant ECO between working and pilot is normal. What is not normal is treating a working lot as near-production acceptance while still changing stack, finish, and AVL every week.
Cost of skipping. Shipping “visual” boards straight into customer pilots without a working stage burns political capital: field failures teach the same lessons a lab script would have caught — at freight and reputation cost.
Stage 4 — Near-production functional: prove pilot readiness
A functional prototype at near-production maturity is as close as practical to the finished product: materials, finishes, process windows, and acceptance depth that will ride into pilot. Finishing touches may still trim cost, but silent swaps are not “finishing touches.”
For a China fab buyer, this stage should prove:
- Laminate/Tg, copper, finish, and mask that pilot will actually buy — stock vs buy called out.
- Process path continuity: same Class language, same test depth family, same packing notes you will reuse.
- Assembly process readiness: paste, reflow, selective/wave map, and inspection depth that match pilot — not a one-off hand-build that cannot scale.
RFQ gates that belong here. Full fab + assembly field table; coupon or sample depth when Class 3 is real; thermal, EMI, reliability, environmental, or mechanical legs only if the end use requires them — named as optional adders, not assumed inside a commodity proto price; freeze rule for ECO after award. When schedule is tight and files can freeze, quick turn PCB capacity can compress calendar after maturity is clear — it does not replace stage proofs.
Cost of skipping. Jumping from PoC or soft Gerber straight to “production-like” functional language is the expensive skip: you pay near-production process and kit cost while still discovering PoC-level topology failures. Pilot then inherits unfrozen AVL and finish fights.
Lab and test gates that belong on the RFQ (by maturity)
Competitor-style lists dump every lab noun — electrical, functional, thermal, EMI, reliability, environmental, mechanical, compliance — onto “the prototype.” Buyer practice assigns gates to maturity so quotes stay comparable.
| Gate family | PoC | Visual / Gerber | Working | Near-production functional |
|---|---|---|---|---|
| Continuity / ET | Optional / smoke | Yes (depth named) | Yes on bare before populate when risk high | Yes; match pilot depth |
| Functional script | Core function only | Usually N/A (bare) | Required | Required + pilot-like coverage |
| Thermal / EMI / env | Only if that is the PoC risk | Rare | Targeted | As end-use requires; as adders |
| AOI / X-ray | N/A or minimal | N/A (bare) | Yes for populated risk | Match pilot |
| Class / coupons | Often deferred | Fab class if rejecting | Fab + A-610 | Full traveler language |
Write gates as traveler rows, not as prestige adjectives. “Reliability tested” without a named standard, duration, or sample plan is theater. Paste depth into the same RFQ table every bidder sees.
Benefits that actually catch cost (not brochure slogans)
Benefit 1 — Catch topology risk before stack spend. PoC and early working proofs stop multilayer and HDI money from funding a function that was never viable.
Benefit 2 — Catch geometry and DFM before populate. Visual / Gerber builds move fab-side mistakes out of assembly scrap. CAM honesty early is cheaper than populated rework.
Benefit 3 — Catch process and kit risk before pilot. Working and near-production stages force Class, finish, AVL, and inspection depth into writing — the same fields you will need when you How to Place an Order for pilot without inventing missing notes.
Benefit 4 — Reduce revision thrash on the expensive lots. Revisions still happen; they happen on the cheapest maturity that can teach the lesson. Skipping stages does not remove revisions — it moves them onto thicker stacks and fuller kits.
Benefit 5 — Make China fab quotes comparable. Named stage + named proof + named gates beats a single “prototype” SKU when three bidders return unlike scopes. Soft “saves time / saves money” claims are true only when maturity is explicit.
None of these benefits require inventing plant TAT badges or certificate menus. They require discipline on the RFQ.
Cost of skipping stages — a short buyer map
- Skip PoC → go straight to near-production functional: high probability of paying pilot-like process cost for topology failures.
- Skip Gerber / visual → populate first: fab geometry errors appear as assembly yield pain and blame loops between fab and PCBA.
- Skip working → customer or field pilot: political and freight cost; lessons that belonged in a lab script.
- Skip near-production freeze → launch pilot on soft AVL/finish: silent substitutions and Class arguments mid-lot; respin funded as “surprises.”
Schedule pressure is real. The answer is not to delete stages; it is to name which proof each lot owns, compress calendar only after freeze, and refuse to buy near-production process for PoC questions.
Soft next step
If you know which maturity you are buying — PoC, visual/Gerber, working, or near-production functional — write the proof goal, the lab/test gates for that stage, Class and finish language, kit ownership, and freeze/EQ rules on one RFQ table. Attach a manufacturing package that matches the stage. XFPCB can respond on that stage checklist when commercial fit is clear — without brochure benefits standing in for traveler acceptance on your lot.