Procurement teams ask for "full testing" and still receive boards that look perfect, pass a soft traveler check, then fail at bring-up. The usual failure mode is not a missing machine on the line. It is a blurred RFQ: inspection treated as electrical proof, bare-board e-test skipped or sampled, ICT fixtures ordered too late, or FCT written as "power on and see."
This guide is a buyer decision matrix for PCB and PCBA testing methods — which gate belongs on the bare panel, which belongs after SMT, where AOI and X-ray sit (and what they do not replace), when fixture NRE pays back by volume, what to put in a China fab/PCBA RFQ so quotes are comparable, and how IPC Class 2 vs Class 3 should change test depth expectations. It is not a machine brochure and not a lab procedure rewrite. Confirm coverage, nets, and pass/fail limits on your drawing and PO; method names alone are not acceptance criteria.
Separate three jobs before you pick a method
Buyers often collapse three different questions into one line item called "test":
- Is the bare board electrically intact? Opens, shorts, and (sometimes) limited net integrity before any parts are placed.
- Were the right parts placed and soldered without catastrophic process defects? Structural and soldering defects after assembly.
- Does the assembled unit do what the product requires under power? Firmware, interfaces, loads, timing — the customer's definition of "works."
Method choice fails when those jobs are mixed. A beautiful AOI report does not prove net continuity on a dense multilayer. A bed-of-nails ICT program does not prove that the radio link meets your RFQ. Flying probe on a bare board does not prove that a BGA solder joint under the package is sound.
Hold the stack in this order when you write the traveler:
- Bare-board electrical test — flying probe or bed-of-nails fixture on the unpopulated panel.
- Post-assembly inspection — SPI where paste matters, AOI for visible solder/placement, X-ray for hidden joints.
- Post-assembly electrical / structural test — ICT or flying probe on the populated board when DFT and volume justify it.
- Functional circuit test (FCT) — powered product behavior with defined stimuli and limits.
- Release gates — first-article checks and lot sampling that confirm the traveler, not substitute for the gates above.
If your quote only says "AOI + FCT" with no bare-board e-test note, you have already decided that fab opens are an SMT problem.
Bare-board electrical test — flying probe vs bed-of-nails
Bare-board e-test answers a narrow question: does the finished copper match the netlist well enough to ship into assembly? Two common tools:
Flying probe (bare board)
Probes move to test points under software control. No custom nail fixture. Setup is mostly CAM + program time. Per-board cycle time is longer than a fixture press. Best fit for prototypes, ECO-heavy revisions, and mid/low volume where fixture NRE would dominate. Coverage depends on accessible pads/vias and the program — "flying probe" on a quote is not automatically 100% netlist if access is incomplete.
Bed-of-nails / fixture e-test (bare board)
A custom fixture contacts many nets at once. High up-front NRE and longer fixture lead time; very fast cycle time once running. Best fit when the design is stable and monthly volume amortizes the fixture. Design changes that move pads can force fixture rework — lock revision timing before you cut metal.
Buyer rule of thumb (not a price list): if you expect few boards and several Gerber revisions, flying probe usually wins on total cost and schedule. If you expect thousands of identical panels and a frozen layout, fixture e-test usually wins on cost-per-board after payback. Ask the fab to state coverage %, netlist source, and whether isolated nets or connector pins are out of reach — not just "e-test included."
Dense HDI, via-in-pad, and buried nets change access. Do not assume the same coverage you got on a four-layer through-hole board.
Assembled ICT vs flying probe vs FCT
After SMT, electrical options shift:
In-circuit test (ICT)
Bed-of-nails or equivalent probing of the populated board to check opens/shorts, presence/value of many components, and sometimes limited digital signatures. Strong process feedback when DFT provides pads and the design is stable. Fixture cost and lead time are real. ICT does not equal full product function — it can pass while firmware, clocks, or RF still fail FCT.
Flying probe on assembled boards
Lower fixture NRE, slower throughput, useful for early lots and revision churn. Access and component height still limit coverage. Treat it as a bridge, not a permanent substitute for ICT on high-volume frozen designs unless you have measured cycle time against ship rate.
Functional circuit test (FCT)
Power the board (or product) and exercise interfaces against written pass/fail limits: voltages, currents, communications, sensors, loads, timing windows. FCT proves product intent; it is weak at pinpointing which resistor drifted unless the fixture and script were built for diagnostics. Customer-defined FCT without limits is theater — "power on OK" is not a limit.
Pairing matters. Many programs use AOI/X-ray for process defects, ICT or flying probe for structural/electrical process feedback, and FCT for release. Skipping the middle layer to "save" money often moves debug into FCT, where diagnosis is slower and scrap more expensive.
Where AOI and X-ray sit — inspection is not electrical proof
AOI and X-ray are inspection methods. They catch many soldering and placement defects early. They do not replace bare-board e-test, ICT, or FCT.
| Method | What it is good at | What it does not prove |
|---|---|---|
| SPI | Paste volume/alignment before place | Component value, opens in copper, product function |
| AOI | Visible solder bridges, missing/wrong polarity parts, many placement defects | Hidden BGA joints, electrical net integrity, firmware behavior |
| X-ray (2D/3D) | Hidden joints, voids, some BGA/QFN issues | Full netlist continuity, parametric limits under load |
| Bare e-test | Opens/shorts vs netlist on bare copper | Solder quality after SMT, powered function |
| ICT | Many component/connection faults on assembled boards | Full system function, RF/link performance unless scripted |
| FCT | Product behavior under defined stimuli | Root-cause of a single tombstone without other gates |
The buyer mistake that shows up most in China PCBA quotes is "AOI + visual = tested." Looking good is not the same as connected, and connected is not the same as working. Write inspection and electrical/FCT as separate lines with scope. If X-ray is sample-only, say sample size and which packages. If AOI is "standard," ask which defect classes are detected vs reported vs escaped.
When fixture cost pays back by volume
Fixture economics are where thin guides stay vague and RFQs go wrong. Use a simple decision frame on every quote comparison:
Prefer flying probe / soft fixture first when:
- Quantity is prototype or low hundreds per revision.
- Layout still moves (ECO risk high).
- Time-to-first-article beats cost-per-board.
- DFT pads for ICT were never designed in.
Plan ICT (or bare bed-of-nails) when:
- Monthly volume is high enough that probe time becomes a bottleneck.
- Design freeze is credible (revision money is already spent).
- DFT pads and keep-outs were designed for nails.
- You need fast process feedback into SMT, not only end-of-line FCT.
Payback thinking (qualitative): compare fixture NRE + fixture LT against (flying-probe cycle time × labor/overhead × remaining volume) plus the cost of late escapes. If the design will change twice more this quarter, do not buy the nails yet. If the design is frozen and you will run the same panel for a year, delaying the fixture to "save NRE" often costs more in probe time and missed shorts.
Also price the soft costs: fixture storage, ECO rework, spare fixtures for a second line, and who owns golden boards. A cheap fixture quote that ignores ECO rules is not cheap.
Class 2 vs Class 3 — test depth, not a sticker
IPC Class 2 vs Class 3 is an acceptance and reliability expectation, not a magic test menu. Buyers still misuse it as a slogan on the RFQ.
Practical expectation shifts (confirm on drawing/PO — do not invent from marketing):
- Class 2 programs often accept a balanced mix: solid bare-board e-test, AOI with defined escape policy, and FCT scoped to product risk. ICT appears when volume/DFT justify it.
- Class 3 (or equivalent high-reliability intent) usually demands tighter documentation of coverage, lower tolerance for untested nets, clearer first-article and change control, and often deeper inspection on critical packages. "Class 3" without coverage %, sampling plans, and failure disposition is still a soft quote.
Do not assume Class 3 automatically includes 100% X-ray, ICT, and boundary scan. Write the gates. If the product is Class 2 commercially but field failure is expensive, buy the test depth you need — class label alone will not force the factory to invent pads or fixtures.
What to write in a China fab / PCBA RFQ
Overseas buyers lose weeks when two China quotes both say "testing included" and mean different travelers. Force comparable lines:
Bare fab RFQ
- Electrical test: flying probe or fixture; coverage % or "100% netlist"; source of netlist; out-of-reach nets policy.
- Any impedance coupon/report ownership (separate from e-test, but often confused on quotes).
- Packing and lot ID so failed lots can be traced.
PCBA RFQ
- SPI / AOI / X-ray: 100% vs sample; packages covered by X-ray; defect classes reported.
- ICT or assembled flying probe: yes/no; fixture ownership; DFT assumptions; coverage goals.
- Boundary scan / JTAG: if used, which chains, who provides vectors.
- Programming: who flashes, which file revision, checksum/verify method.
- FCT: fixture ownership, stimuli list, numeric pass/fail limits, golden unit policy, data logging format.
- First-article / FAI expectations before the production lot.
- Failure disposition: stop-ship thresholds, NCMR path, who pays for debug hours.
Procurement habit: send the same test matrix to every bidder. Score what is in the base price vs extra. A low unit price that moves FCT limits to "TBD after EVT" is not a complete quote.
China factories move quickly when coverage and limits are locked and a named engineer answers EQ. They do not replace missing DFT with goodwill. Chat approvals are not revision control — put the test matrix on the PO with the file set revision.
Volume economics in China fab/PCBA often look different from a domestic NRE spreadsheet. Probe time is cheap relative to Western labor rates, so flying probe can stay attractive longer into volume — until ship-rate, fixture amortization, and escape cost flip the math. Conversely, fixture shops can be fast when DFT is clean, but ECO rework on nails still burns calendar. Ask each bidder for a simple break-even sketch: at what monthly quantity their ICT (or bare fixture) quote undercuts flying probe for your board, including fixture LT. If they cannot answer without inventing a number, treat "fixture recommended" as a sales default, not an engineered payback.
One more RFQ hygiene item: require the vendor to list excluded nets and packages on the quote acknowledgment. Silence here is how "100% tested" becomes "everything we could reach." Attach that exclusion list to the PO revision so EVT and production use the same definition of done.
Soft next step
If you are building or refreshing a test plan now, draft a one-page method matrix: bare e-test type + coverage, inspection gates (SPI/AOI/X-ray scope), ICT or assembled probe decision with volume/payback note, FCT limits ownership, Class intent, and which lines are base vs optional on the RFQ.
Share that matrix with the Gerbers, BOM, and DFT notes when you ask a China fab or PCBA house to quote. Comparable scope beats a race to the cheapest "full test" checkbox — and it keeps inspection from being mistaken for electrical proof.