What Is the PCB Fabrication Process? Buyer Primer on Quality, Cost & Assembly Risk

Buyers searching "what is the PCB fabrication process" often land on a chemistry brochure: photoresist, etch, laminate, drill, plate, mask, finish, test. Those steps are real. They are not what usually burns schedule or scrap money. What burns them is treating bare-board fab as a commodity ZIP-and-quote exercise, then discovering at SMT that the boards were built on assumptions you never locked.

This primer is for procurement, hardware leads, and product owners who need a buyer definition of PCB fabrication — how it differs from assembly, why fab quality shows up as assembly scrap, which quote fields actually move price and lead time, which supplier questions expose real process control, and how China fab quoting often hides defaults behind a low number. It is not a full process-lab walkthrough. Confirm stackup, finish, class, and test notes on your drawing; stage lists are not RFQ fields.

Fabrication vs assembly — separate jobs, one scrap bill

PCB fabrication turns design data into a finished bare board: copper layers laminated and patterned, holes drilled and plated, solder mask and surface finish applied, legend printed, board electrically tested, and packed. No components. No firmware. No functional product yet.

PCB assembly (PCBA) places and solders components onto that bare board, then typically programs, inspects, and functionally tests the populated unit.

Buyers mix the two because many suppliers sell both — and because a cheap fab quote can look like project progress. It is not. A board that is "fabbed" but wrong for the paste plan, flatness window, or finish shelf life becomes assembly scrap. You pay for fab again, BOM again, and often a schedule slip that costs more than the panel.

Hold this distinction when you compare vendors:

• Fab RFQ answers: stackup, materials, finish, IPC class, e-test, coupon/report expectations, packing.
• Assembly RFQ answers: BOM, paste/stencil, placement class, AOI/X-ray plan, programming, FCT limits.
• Turnkey quotes bundle both — still force the fab assumptions into writing, or the assembler inherits silent defaults.

If your team only reviews the assembly traveler and treats fab as "standard FR-4, whatever finish," you have already decided that process control is optional.

Why fab quality matters before the first paste print

Poor fab rarely announces itself as a dramatic open on every board. It shows up as yield noise and field risk that procurement struggles to attribute:

• Unclear files / missing notes → CAM guessing, EQ loops, quote revisions after the PO is already cut.
• Tolerance and registration drift → solder-mask misalignment, annular-ring marginality, vias that pass a soft e-test and fail after thermal cycles.
• Finish and solderability mismatch → wetting problems after warehouse time, or coplanarity issues on fine-pitch BGA.
• Warp / copper imbalance → paste print and placement variation that looks like an SMT process problem.
• Material substitution without SI/Tg check → "same Gerber" lots that behave differently on the bench.
• Weak plating or thin copper in holes → intermittent opens that pass flying probe cold and fail in the field.

From a buyer's seat, fab quality is not a lab aesthetic. It is procurement risk: how much of your assembly budget you are betting on undocumented defaults. The more layers, impedance, HDI, or fine pitch you carry, the less "standard process" means anything useful.

Clarify before you request a quote

A useful quote is a mirror of locked intent — not a race to the lowest unit price on incomplete data. Before you send the RFQ, be able to answer:

1. Build intent — prototype, quick-turn bridge, or production? Quantity and revision stability change panelization and test fixture economics.
2. Electrical / reliability intent — controlled impedance, RF, high current, high-Tg / lead-free assembly, IPC Class 2 vs Class 3, any conformal-coat or harsh-environment notes that drive material and finish.
3. Construction — layer count, board thickness, copper weights, via types (through, blind/buried, microvia), via-in-pad / fill needs.
4. Materials — laminate family or approved alternates (not bare "FR-4" if Tg, halogen-free, or Dk/Df matters).
5. Finish and mask — finish chosen for pitch, reflow cycles, and shelf life; mask color secondary to opening/dam rules and via treatment.
6. Inspection and documentation — AOI scope, 100% e-test vs sample, impedance coupon/report ownership, CoC / material cert expectations, packing and humidity control.

If you cannot answer these, the factory will answer for you — usually with the cheapest compliant-looking defaults. Two vendors quoting the same ZIP can then diverge by 30–50% not because one is "better," but because one assumed OSP + Class 2 + no coupon report, and the other priced ENIG + impedance control + 100% netlist test.

Procurement habit: Same clarification checklist to every bidder. Otherwise you compare optimism, not process.

Which quote fields move price and lead time

Buyers do not need every etch chemistry. They need to know which RFQ fields change money and calendar. The table below is a practical map — not a price list.

Two boards that "look similar" on a screenshot can quote differently because one row in this table was locked and the other was left as "standard." When a quote is dramatically lower, ask which rows were treated as TBD.

How fab quality shows up as assembly scrap

Fabrication and assembly are coupled whether your PO is turnkey or split. Bare-board defects that pass a soft fab visual often become SMT scrap or debug time:

• Solder-mask registration — dams too thin or openings shifted → bridges on fine pitch; assembler blames stencil while the mask was already wrong.
• Surface finish — wrong finish for pitch or shelf life → non-wetting, head-in-pillow, or forced bake/rework after storage.
• Hole plating quality — thin or voided plating → intermittent via opens after reflow or thermal shock.
• Board flatness — warp from copper imbalance or poor lamination → paste volume variation and tombstoning that looks like a reflow recipe issue.
• Dimensional / outline accuracy — boards that do not seat in fixtures or enclosures → line stops and mechanical scrap.
• Via-in-pad without fill/cap notes — paste wicking and voids under BGA that AOI on the bare board never saw.

Treat fab notes as assembly-readiness inputs. Finish, mask via treatment, flatness expectations, and moisture packing should match the paste plan and warehouse plan you already intend to run. If fab and assembly are different companies, put the same notes on both RFQs so nobody can claim the other "should have known."

Supplier questions that expose real process control

Price and glossy capability pages do not prove control. Ask questions that force concrete answers:

• Do you run DFM / CAM review before releasing the traveler, and how are engineering questions tracked to a revision?
• Is AOI included for inner and outer layers on this construction, or only outer?
• What electrical test is included — flying probe vs fixture, 100% vs sample, repair-vs-scrap policy?
• For impedance jobs: who owns the coupon, what report format ships, and is the stackup approved in writing before build?
• Which IPC acceptance class is quoted, and where is it written on the fab drawing / PO?
• What finish thickness / shelf-life guidance do you give for the finish you quoted?
• What packing (vacuum, desiccant, HIC) and lot traceability come with the shipment?
• If material alternates are allowed, how do you get buyer approval before substituting laminate?

Vague answers ("we follow IPC," "standard AOI," "usual FR-4") are a signal. Strong suppliers answer with what is in the quote and what is extra, and they refuse to silently upgrade Class or laminate because the product "looks important."

Use the same question set on every shortlist vendor. Score the answers, not the brochure.

If fab and SMT are split across borders, add Incoterms, moisture-sensitivity handling for the finish you chose, and who owns incoming inspection criteria for warp and finish. Ambiguity here creates finger-pointing after the panels land — not better boards.

China fab quoting reality — assumptions vs locked notes

Overseas buyers sourcing from China fabs (or China fab feeding overseas SMT) hit a pattern: the low quote is often a bundle of defaults, not a reading of your intent.

Common silent assumptions:

• Generic FR-4 Tg when you meant high-Tg for lead-free or a named low-loss family.
• OSP or lead-free HASL when the layout needs ENIG flatness for fine BGA.
• Class 2 acceptance when reliability notes imply Class 3 plating/annular expectations.
• Impedance "supported" without coupon ownership or report.
• Sample e-test or soft netlist coverage on dense multilayer.
• Material brand flexibility without a written alternate list.

China fab teams are usually fast when notes are locked and a named technical contact answers EQ in one revision cycle. They are not mind readers. Chat screenshots are not revision control. If the PO still says Rev A, Rev A gets built — even if someone emailed a "final" Gerber last Tuesday.

Lock notes on the RFQ and PO together: stackup or approved alternates, finish, IPC class, impedance coupon/report, e-test coverage, packing, and file revision. When two quotes diverge wildly, ask each vendor to list assumed defaults. The honest list is more valuable than the unit price.

For complex boards, expect an engineering-question loop. Budget calendar time for it. An unanswered EQ parks the traveler; a vague "use whatever you have" answer creates boards that pass fab FQC and fail SI or wetting later.

One more procurement habit: keep a quote comparison matrix with the same rows as the cost/lead table above. Fill each vendor's assumed defaults in writing. When a line is blank, treat it as risk — not as a free upgrade you will get later for goodwill. Boards that ship "close enough" still consume assembly fixtures, operator time, and sometimes customer trust when the first lot fails wetting or SI.

Soft next step

If you are preparing a fab RFQ now, start with a one-page intent lock: build stage, layer/stack notes, material family or alternates, finish and shelf plan, IPC class, impedance/coupon ownership, e-test coverage, and packing/docs. Send that sheet with the Gerbers to every bidder.

When you need a China fab to price against locked notes — not silent defaults — share the package and the open technical questions. A clear RFQ is the cheapest process control you can buy before paste ever hits the board.