Drill QA is not “holes look round.” It is a short list of measurable accepts that decide whether electroless copper and electrolytic plating can trust the wall—and whether first article proves the traveler. Process controls (stack, hit count, entry) were the previous post; this one is what to measure, what to reject, and what belongs on the PO / FAI pack. No universal Cpk or micron tables pretending every laminate shares one limit.
Separate drill size from finished hole
After mechanical drill—and before metallization—inspect drill diameter. Finished PTH size later includes copper on the wall, so it is smaller. Mixing the two on a pin-gauge plan is a classic FAI fight. On the PO:
- State whether diameter checks are on as-drilled or finished holes (and at which process gate).
- Name the gauge method you will accept (pins, vision, sample microsection)—not five conflicting methods.
Position accuracy is a second metric: hole center vs design (and vs inner pads after scale compensation). Capability indices are plant language; buyers should freeze annular-ring / breakout rules and sample size on FAI, not a blog’s single Cpk slogan.
Wall condition that plating will inherit
Four wall/substrate issues dominate later PTH failures:
- Roughness / smear — resin smear and torn glass leave a wall electroless copper may not wet or bond. Cross-section direction vs glass weave changes what you “see”; agree the section method with the fab for any roughness or smear callout.
- Nail-heading — inner copper pushed sideways by a dull or overloaded bit. Evaluate on microsection; acceptance is usually tied to copper thickness, not a freehand “looks bad.”
- Burrs — entry/exit copper lips that become plating spikes. Often entry/backup and hit-count related (process article), but FAI still needs a burr height / visual gate if cosmetics or fine pitch matter.
- Plugged chips — debris left in the hole blocks chemistry. Treat as critical; do not ship “mostly clear” barrels into electroless.
Haloing (white ring / laminate fracture around the hole) and fiber wicking into glass bundles are reliability flags, especially for harsh environments. They are not fixed by more copper. Call them out when your class of product cares; otherwise the plant’s internal scrap criteria still apply.
Plating readiness as an explicit gate
Drill QA ends when the hole is ready for desmear → activation → electroless → electrolytic—not when the spindle stops. If your product is plating-critical (high AR, fine vias, impedance coupons that share the drill recipe), require:
- Documented desmear / etch-back expectation for that stack (chemistry family, not a secret sauce dump).
- Sample microsections at FAI showing wall copper continuity and nail-head / smear status.
- Clear disposition: re-drill, scrap, or EQ—never silent “polish and hope.”
What belongs on the PO versus the FAI pack
PO / fab note
- Finished vs drill diameter language and tolerances that actually matter (press-fit, precision NPTH, tight vias).
- Position / annular-ring requirements tied to design rules.
- Any mandatory microsection or plating-thickness witness for the job class.
- Back-drill or controlled-depth features already named as hole classes (taxonomy post).
FAI / first-article pack
- As-drilled diameter and position sample data (method named).
- Cross-sections for smear, nail-heading, wall copper after plating when PTH reliability is in scope.
- Burr / plug / halo findings if those gates were agreed.
- Traveler references for stack, hit count, and entry/backup used on the FAI lot—so production cannot silently change the recipe.
How this differs from process and bit posts
Asking how the plant drills (stack, hits, entry, registration) is process control. Asking what evidence proves the hole is QA. Bit ST/UC and geometry explain why walls degrade; they are not acceptance criteria. Keep the three conversations separate on the EQ so nothing is “assumed standard.”
See Testing & Inspection for the broader evidence menu, Flying Probe Testing for electrical opens/shorts after metallization, and PCB Fabrication Process for where drill sits before plating.
What we are not claiming
No invented Cpk floors, no universal roughness micron limits copied as law, no MIL/GJB clause dump as XFPCB default, and no guarantee that every FR-4 stack meets aerospace nail-head ratios. Agree measurable gates with the fab for your class—then put those gates on the PO and prove them on FAI.